Personal profile
In Korean
우성윤 교수(IT대학 전자공학부)
Education
o (2014) 경북대학교 전자공학부 공학사
o (2021) 서울대학교 전기정보공학부 공학박사 (석박사통합)
o (2021) 서울대학교 전기정보공학부 공학박사 (석박사통합)
Professional Experience
o (2023~현재) 경북대학교 IT대학 전자공학부 조교수
o (2021~2023) 삼성전자 메모리사업부 DRAM 공정 설계 책임 연구원
o (2021~2023) 삼성전자 메모리사업부 DRAM 공정 설계 책임 연구원
Research Interests
휘발성/비휘발성 메모리(FLASH, DRAM), 신경모방소자 및 시스템, 방사선 영향 평가, SiC기반 전력반도체
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Collaborations and top research areas from the last five years
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Analysis of Grain Boundary Effects Based on Location in a Diode-Type NAND Flash Memory Cell
Kim, J., Kim, H., Moon, H., Song, W., Bae, J. H., Choi, N. & Woo, S. Y., 2025, 2025 Silicon Nanoelectronics Workshop, SNW 2025. Institute of Electrical and Electronics Engineers Inc., p. 76-77 2 p. (2025 Silicon Nanoelectronics Workshop, SNW 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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CMOS-compatible flash-gated thyristor–based neuromorphic module with small area and low energy consumption for in-memory computing
Ko, J., Im, J., Kim, J., Shin, W., Koo, R. H., Park, S. H., Woo, S. Y. & Lee, J. H., 18 Jul 2025, In: Science advances. 11, 29, eadt8227.Research output: Contribution to journal › Article › peer-review
Open Access6 Scopus citations -
Comparative Analysis of Grain Boundary Effects in FET-Type and Diode-Type 3-D nand flash memory
Kim, J., Kim, H., Im, J., Lee, S. T., Kwon, D., Choi, N. & Woo, S. Y., 2025, In: IEEE Transactions on Electron Devices. 72, 10, p. 5428-5435 8 p.Research output: Contribution to journal › Article › peer-review
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Design Optimization of SiC CMOS FinFET for High-Temperature Next-Generation SoC Logic Applications
Kwon, T. S., Kim, Y. J., Kim, H. W., Yoon, Y. J., Seo, J. H. & Woo, S. Y., 2025, 2025 Silicon Nanoelectronics Workshop, SNW 2025. Institute of Electrical and Electronics Engineers Inc., p. 56-57 2 p. (2025 Silicon Nanoelectronics Workshop, SNW 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory
Kwon, D., Woo, S. Y., Hwang, J., Kim, H., Bae, J. H., Shin, W., Park, B. G. & Lee, J. H., 2025, In: IEEE Transactions on Neural Networks and Learning Systems. 36, 1, p. 807-819 13 p.Research output: Contribution to journal › Article › peer-review
2 Scopus citations