Research output per year
Research output per year
Personal profile
In Korean
김선민 교수(IT대학 전자공학부)
Education
o (2016) B.S., Ulsan National Institute of Science and Technology
o (2018) M.S., Ulsan National Institute of Science and Technology
o (2021) Ph.D., Ulsan National Institute of Science and Technology
o (2018) M.S., Ulsan National Institute of Science and Technology
o (2021) Ph.D., Ulsan National Institute of Science and Technology
Professional Experience
o (2023~Present) Assistant professor, Kyungpook National University, Daegu, Korea
o (2021~2023) Postdoctoral researcher, POSTECH, Gyeongbuk, Korea
o (2018~2021) Doctoral researcher, POSTECH, Gyeongbuk, Korea
o (2021~2023) Postdoctoral researcher, POSTECH, Gyeongbuk, Korea
o (2018~2021) Doctoral researcher, POSTECH, Gyeongbuk, Korea
Research Interests
o Processing in Memory (PIM) based AI chip design
o System on Chip (SoC) design
o VLSI Computer-aided Design (CAD)
o System on Chip (SoC) design
o VLSI Computer-aided Design (CAD)
Major Research Achievements
o (Nature Electronics) Tunnelling-based ternary metal–oxide–semiconductor technology
o (ACS Nano) Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems I) A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems II) Optimizing Ternary Multiplier Design with Fast Ternary Adder
o (IEEE Transactions on Circuits and Systems II) Low-power Ternary Multiplication Using Approximate Computing
o (ACS Nano) Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems I) A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems II) Optimizing Ternary Multiplier Design with Fast Ternary Adder
o (IEEE Transactions on Circuits and Systems II) Low-power Ternary Multiplication Using Approximate Computing
url
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Collaborations and top research areas from the last five years
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Junctionless Negative-Differential-Resistance Device Using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing
Lee, T., Jung, K. S., Seo, S., Lee, J., Park, J., Kang, S., Park, J., Kang, J., Ahn, H., Kim, S., Lee, H. W., Lee, D., Kim, K. S., Kim, H., Heo, K., Kim, S., Bae, S. H., Kang, S., Kang, K. & Kim, J. & 1 others, , 13 Jun 2024, In: Advanced Materials. 36, 24, 2310015.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations -
Optimizing Ternary Multiplier Design With Fast Ternary Adder
Yoon, J., Baek, S., Kim, S. & Kang, S., 1 Feb 2023, In: IEEE Transactions on Circuits and Systems II: Express Briefs. 70, 2, p. 766-770 5 p.Research output: Contribution to journal › Article › peer-review
6 Scopus citations -
Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
Lee, Y., Kim, S., Lee, H. I., Kim, S. M., Kim, S. Y., Kim, K., Kwon, H., Lee, H. W., Hwang, H. J., Kang, S. & Lee, B. H., 26 Jul 2022, In: ACS Nano. 16, 7, p. 10994-11003 10 p.Research output: Contribution to journal › Article › peer-review
Open Access14 Scopus citations -
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor
Kam, D., Min, J. G., Yoon, J., Kim, S., Kang, S. & Lee, Y., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 1077-1082 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Open Access2 Scopus citations -
Design and analysis of a low-power ternary SRAM
Choi, Y., Kim, S., Lee, K. & Kang, S., 2021, 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9401259. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2021-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
11 Scopus citations