Personal profile
In Korean
김선민 교수(IT대학 전자공학부)
Education
o (2016) B.S., Ulsan National Institute of Science and Technology
o (2018) M.S., Ulsan National Institute of Science and Technology
o (2021) Ph.D., Ulsan National Institute of Science and Technology
o (2018) M.S., Ulsan National Institute of Science and Technology
o (2021) Ph.D., Ulsan National Institute of Science and Technology
Professional Experience
o (2023~Present) Assistant professor, Kyungpook National University, Daegu, Korea
o (2021~2023) Postdoctoral researcher, POSTECH, Gyeongbuk, Korea
o (2018~2021) Doctoral researcher, POSTECH, Gyeongbuk, Korea
o (2021~2023) Postdoctoral researcher, POSTECH, Gyeongbuk, Korea
o (2018~2021) Doctoral researcher, POSTECH, Gyeongbuk, Korea
Research Interests
o Processing in Memory (PIM) based AI chip design
o System on Chip (SoC) design
o VLSI Computer-aided Design (CAD)
o System on Chip (SoC) design
o VLSI Computer-aided Design (CAD)
Major Research Achievements
o (Nature Electronics) Tunnelling-based ternary metal–oxide–semiconductor technology
o (ACS Nano) Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems I) A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems II) Optimizing Ternary Multiplier Design with Fast Ternary Adder
o (IEEE Transactions on Circuits and Systems II) Low-power Ternary Multiplication Using Approximate Computing
o (ACS Nano) Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems I) A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
o (IEEE Electron Device Letters) Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
o (IEEE Transactions on Circuits and Systems II) Optimizing Ternary Multiplier Design with Fast Ternary Adder
o (IEEE Transactions on Circuits and Systems II) Low-power Ternary Multiplication Using Approximate Computing
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Collaborations and top research areas from the last five years
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LW-ResGRU DPD: Layer-Wise Residual GRU for Low-Latency DPD in Nonlinear RF Systems
Kim, D., Park, S. & Kim, S., 2026, In: IEEE Transactions on Circuits and Systems II: Express Briefs. 73, 2, p. 153-157 5 p.Research output: Contribution to journal › Article › peer-review
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An area and power efficient ternary serial adder using phase composite ZnO stack channel FETs
Kim, K., Kim, S., Kim, S. Y., Lee, Y., Lee, H. W., Kang, S. & Lee, B. H., 8 Apr 2025, In: Nanoscale Advances. 7, 11, p. 3508-3513 6 p.Research output: Contribution to journal › Article › peer-review
Open Access -
An RTL-Based General Synthesis Methodology for Device-Independent Ternary Logic Circuits
Park, H., Kim, S., Kim, S. & Song, T., 2025, In: IEEE Access. 13, p. 163648-163660 13 p.Research output: Contribution to journal › Article › peer-review
Open Access -
Area- and Energy-Efficient Ternary D Flip-Flop Design
Kim, T. & Kim, S., May 2024, In: Journal of Sensor Science and Technology. 33, 3, p. 134-138 5 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations -
Configurable anti-ambipolar photoresponses for optoelectronic multi-valued logic gates
Cui, X., Kim, S., Ahmed, F., Du, M., Liapis, A. C., Muñoz, J. A., Shafi, A. M., Uddin, M. G., Ali, F., Zhang, Y., Kang, D. H., Lipsanen, H., Kang, S., Yoon, H. H. & Sun, Z., 29 Jul 2024, In: Applied Physics Letters. 125, 5, 051105.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations