Research output per year
Research output per year
Personal profile
In Korean
송대건 교수(IT대학 전자공학부)
Education
(2007) B.A., Yonsei University
(2009) M.A., KAIST
(2015) Ph.D., Georgia Institute of Technology, USA
(2009) M.A., KAIST
(2015) Ph.D., Georgia Institute of Technology, USA
Professional Experience
(2019 ~ Present) Assistant Professor, Kyungpook National University, Daegu
(2016 -2019) Senior R&D Engineer, Synopsys Inc., USA
(2015) Software Intern, Cadence Design Systems, USA
(2014) Intern, Synopsys Inc., USA
(2010) Researcher, KAIST
(2016 -2019) Senior R&D Engineer, Synopsys Inc., USA
(2015) Software Intern, Cadence Design Systems, USA
(2014) Intern, Synopsys Inc., USA
(2010) Researcher, KAIST
Research Interests
Advanced Technology Nodes in Semiconductors
Processing in Memory, Analog Compute-in-Memory
Ternary Logic Circuits
Digital VLSI
Computer Aided Design and Automation
Processing in Memory, Analog Compute-in-Memory
Ternary Logic Circuits
Digital VLSI
Computer Aided Design and Automation
Major Research Achievements
First Complementry FET (CFET) standard cell designs and transistor models
First Forksheet FET design library for analog and digital circuits
First Nanosheet FET design library for analog and digital circuits
Circuits and design methodology development for Ternary Logic
Methodology and Analysis for 3-dimensional integrated circuits
First Forksheet FET design library for analog and digital circuits
First Nanosheet FET design library for analog and digital circuits
Circuits and design methodology development for Ternary Logic
Methodology and Analysis for 3-dimensional integrated circuits
url
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Collaborations and top research areas from the last five years
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Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs
Lee, H., Kim, S., Kim, J., Jeong, J., Yang, J. & Song, T., 2025, In: IEEE Access. 13, p. 1193-1207 15 p.Research output: Contribution to journal › Article › peer-review
Open Access -
Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node
Jeong, J., Shin, Y., Lee, H., Ko, J., Kim, J. & Song, T., 2024, In: IEEE Access. 12, p. 97557-97571 15 p.Research output: Contribution to journal › Article › peer-review
Open Access -
FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond
Shin, Y., Park, D., Koh, D., Heo, D., Park, J., Lee, H., Kim, J., Lee, H. & Song, T., 2024, ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
2 Scopus citations -
Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction
Woo, S., Lee, H., Shin, Y., Han, M. S., Go, Y., Kim, J., Lee, H., Kim, H. & Song, T., 2024, 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings -Design, Automation and Test in Europe, DATE).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
Robust Hardware Trojan Detection Method by Unsupervised Learning of Electromagnetic Signals
Lee, D., Lee, J., Jung, Y., Kauh, J. & Song, T., 2024, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32, 12, p. 2327-2340 14 p.Research output: Contribution to journal › Article › peer-review
Open Access2 Scopus citations