Personal profile
In Korean
정연배 교수(IT대학 전자공학부)
Education
o (1995) Ph.D., University of Florida, USA
o (1986) M.S., Korea Advanced Institue of Science and Technology, Rep. of Korea
o (1984) B.S., Korea Aerospace University, Rep. of Korea
o (1986) M.S., Korea Advanced Institue of Science and Technology, Rep. of Korea
o (1984) B.S., Korea Aerospace University, Rep. of Korea
Professional Experience
o (2002~Present) Professor, Kyungpook National University, Rep. of Korea
o (2000~2002) Project Manager, Ramtron International Corporation, USA
o (1995~2000) Principal Engineer, Samsung Electronics Corpoation, Rep. of Korea
o (1991~1995) Research Assistant, University of Florida, USA
o (1986~1990) Research Engineer, Electronics and Telecommunications Research Institute, Rep. of Korea
o (2000~2002) Project Manager, Ramtron International Corporation, USA
o (1995~2000) Principal Engineer, Samsung Electronics Corpoation, Rep. of Korea
o (1991~1995) Research Assistant, University of Florida, USA
o (1986~1990) Research Engineer, Electronics and Telecommunications Research Institute, Rep. of Korea
Research Interests
Memory IC design for future challenges, Process-in-memory desgin beyond von Neumann computing, Computational memory accelerating artificial neural networks, Wearable platform subthreshold on-chip memory, High-performance analog circuitry, High-speed/low-power VLSI systems, Digital IP design for mobile platform architecture, Digitally-assisted multi-functional VLSI systems
Major Research Achievements
o Design and evaluation of logic-compatible multifunctional process-in-memory architecture for AI computing platform
o Development of sub-threshold voltage novel on-chip memory for wearable computing engine
o Technology development of logic-CMOS compatible embedded 2T DRAM
o Design and fabrication of power-efficient dual-path charge pump with standard logic CMOS technology
o Development of small-swing latch based low-power embedded memory
o Development of 4-Mb asynchronous low-power SRAM
o Design of 64-Mb dual-bank read-while-write NOR flash memory
o Technology development of 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme
o Development of physically based predictive lateral DMOS transistor model and circuit simulator for intelligent power IC design
o Design and fabrication of PtSi Schottky barrier IR detector
o Development of sub-threshold voltage novel on-chip memory for wearable computing engine
o Technology development of logic-CMOS compatible embedded 2T DRAM
o Design and fabrication of power-efficient dual-path charge pump with standard logic CMOS technology
o Development of small-swing latch based low-power embedded memory
o Development of 4-Mb asynchronous low-power SRAM
o Design of 64-Mb dual-bank read-while-write NOR flash memory
o Technology development of 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme
o Development of physically based predictive lateral DMOS transistor model and circuit simulator for intelligent power IC design
o Design and fabrication of PtSi Schottky barrier IR detector
url
Fingerprint
Dive into the research topics where Yeonbae Chung is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 1 Similar Profiles
Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
-
A Physical LDMOST Model and Predictive Simulations for Advanced Technology CAD
Chung, Y., Feb 2025, In: SSRG International Journal of Electrical and Electronics Engineering. 12, 2, p. 39-47 9 p.Research output: Contribution to journal › Article › peer-review
Open Access -
Logic-Compatible Embedded DRAM Architecture for Multifunctional Digital Storage and Compute-in-Memory
Kim, T. & Chung, Y., Nov 2024, In: Applied Sciences (Switzerland). 14, 21, 9749.Research output: Contribution to journal › Article › peer-review
Open Access -
A Steady-State LDMOST Model Based on Semi-Numerical Regional Approach
Chung, Y. & Kim, T., 1 Sep 2022, In: International Journal of Emerging Technology and Advanced Engineering. 12, 9, p. 94-101 8 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations -
A novel 8T cell-based subthreshold static ram for ultra-low power platform applications
Kim, T., Manisankar, S. & Chung, Y., Jun 2020, In: Electronics (Switzerland). 9, 6, p. 1-17 17 p., 928.Research output: Contribution to journal › Article › peer-review
Open Access7 Scopus citations -
개선된 메모리 셀을 활용한 문턱전압 이하 스태틱 램 어레이 설계
Yeonbae, C., 2019, In: 전기전자학회논문지.Research output: Contribution to journal › Article › peer-review