2048 Complex point FFT architecture for digital audio broadcasting system

Jun Rim Choi; Soo bok Park; Dong Seok Han; Se Ho Park

doi:10.1109/ISCAS.2000.857580

2048 Complex point FFT architecture for digital audio broadcasting system

Jun Rim Choi, Soo bok Park, Dong Seok Han, Se Ho Park

School of Electronics Engineering

Kyungpook National University

Research output: Contribution to journal › Conference article › peer-review

25 Scopus citations

Abstract

In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding.

Original language	English
Pages (from-to)	V-693-V-696
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2000.857580
State	Published - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000

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10.1109/ISCAS.2000.857580

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title = "2048 Complex point FFT architecture for digital audio broadcasting system",

abstract = "In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding.",

author = "Choi, {Jun Rim} and Park, {Soo bok} and Han, {Dong Seok} and Park, {Se Ho}",

year = "2000",

doi = "10.1109/ISCAS.2000.857580",

language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

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note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

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AU - Choi, Jun Rim

AU - Park, Soo bok

AU - Han, Dong Seok

AU - Park, Se Ho

PY - 2000

Y1 - 2000

N2 - In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding.

AB - In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding.

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DO - 10.1109/ISCAS.2000.857580

M3 - Conference article

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SN - 0271-4310

VL - 5

SP - V-693-V-696

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

ER -

2048 Complex point FFT architecture for digital audio broadcasting system

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