3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

Yeonbae Chung; Mun Kyu Choi; Seung Kyu Oh; Byung Gil Jeon; Kang Deog Suh

3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

Yeonbae Chung, Mun Kyu Choi, Seung Kyu Oh, Byung Gil Jeon, Kang Deog Suh

School of Electronics Engineering

Samsung

Research output: Contribution to conference › Paper › peer-review

13 Scopus citations

Abstract

A 4 mega-bits FRAM with novel design techniques is described. The prototype device incorporating these circuit scheme shows 75 ns access time, 21 mA active current at 3.3 V, 25°C, 110 ns cycle. It measures 116 mm² with 0.6 μm CMOS technology.

Original language	English
Pages	97-98
Number of pages	2
State	Published - 1999
Event	Proceedings of the 1999 Symposium on VLSI Circuits - Kyoto, Jpn Duration: 17 Jun 1999 → 19 Jun 1999

Conference

Conference	Proceedings of the 1999 Symposium on VLSI Circuits
City	Kyoto, Jpn
Period	17/06/99 → 19/06/99

Cite this

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title = "3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme",

abstract = "A 4 mega-bits FRAM with novel design techniques is described. The prototype device incorporating these circuit scheme shows 75 ns access time, 21 mA active current at 3.3 V, 25°C, 110 ns cycle. It measures 116 mm2 with 0.6 μm CMOS technology.",

author = "Yeonbae Chung and Choi, {Mun Kyu} and Oh, {Seung Kyu} and Jeon, {Byung Gil} and Suh, {Kang Deog}",

year = "1999",

language = "English",

pages = "97--98",

note = "Proceedings of the 1999 Symposium on VLSI Circuits ; Conference date: 17-06-1999 Through 19-06-1999",

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T1 - 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

AU - Chung, Yeonbae

AU - Choi, Mun Kyu

AU - Oh, Seung Kyu

AU - Jeon, Byung Gil

AU - Suh, Kang Deog

PY - 1999

Y1 - 1999

N2 - A 4 mega-bits FRAM with novel design techniques is described. The prototype device incorporating these circuit scheme shows 75 ns access time, 21 mA active current at 3.3 V, 25°C, 110 ns cycle. It measures 116 mm2 with 0.6 μm CMOS technology.

AB - A 4 mega-bits FRAM with novel design techniques is described. The prototype device incorporating these circuit scheme shows 75 ns access time, 21 mA active current at 3.3 V, 25°C, 110 ns cycle. It measures 116 mm2 with 0.6 μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=0033280506&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0033280506

SP - 97

EP - 98

T2 - Proceedings of the 1999 Symposium on VLSI Circuits

Y2 - 17 June 1999 through 19 June 1999

ER -

3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

Abstract

Conference

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