3D-MAPS: 3D Massively parallel processor with stacked memory

Dae Hyun Kim; Krit Athikulwongse; Michael Healy; Mohammad Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young Joon Lee; Dean Lewis; Tzu Wei Lin; Chang Liu; Shreepad Panth; Mohit Pathak; Minzhen Ren; Guanhao Shen; Taigon Song; Dong Hyuk Woo; Xin Zhao; Joungho Kim; Ho Choi; Gabriel Loh; Hsien Hsin Lee; Sung Kyu Lim

doi:10.1109/ISSCC.2012.6176969

3D-MAPS: 3D Massively parallel processor with stacked memory

Dae Hyun Kim, Krit Athikulwongse, Michael Healy, Mohammad Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young Joon Lee, Dean Lewis, Tzu Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho ChoiGabriel Loh, Hsien Hsin Lee, Sung Kyu Lim

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

140 Scopus citations

Abstract

Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm ² footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm ² power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

Original language	English
Title of host publication	2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
Pages	188-189
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2012.6176969
State	Published - 2012
Event	59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States Duration: 19 Feb 2012 → 23 Feb 2012

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	55
ISSN (Print)	0193-6530

Conference

Conference	59th International Solid-State Circuits Conference, ISSCC 2012
Country/Territory	United States
City	San Francisco, CA
Period	19/02/12 → 23/02/12

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10.1109/ISSCC.2012.6176969

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Kim, D. H., Athikulwongse, K., Healy, M., Hossain, M., Jung, M., Khorosh, I., Kumar, G., Lee, Y. J., Lewis, D., Lin, T. W., Liu, C., Panth, S., Pathak, M., Ren, M., Shen, G., Song, T., Woo, D. H., Zhao, X., Kim, J., ... Lim, S. K. (2012). 3D-MAPS: 3D Massively parallel processor with stacked memory. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers (pp. 188-189). Article 6176969 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55). https://doi.org/10.1109/ISSCC.2012.6176969

@inproceedings{63f6f85244e54c7dab048ae5a69984df,

title = "3D-MAPS: 3D Massively parallel processor with stacked memory",

abstract = "Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm 2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm 2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.",

author = "Kim, {Dae Hyun} and Krit Athikulwongse and Michael Healy and Mohammad Hossain and Moongon Jung and Ilya Khorosh and Gokul Kumar and Lee, {Young Joon} and Dean Lewis and Lin, {Tzu Wei} and Chang Liu and Shreepad Panth and Mohit Pathak and Minzhen Ren and Guanhao Shen and Taigon Song and Woo, {Dong Hyuk} and Xin Zhao and Joungho Kim and Ho Choi and Gabriel Loh and Lee, {Hsien Hsin} and Lim, {Sung Kyu}",

year = "2012",

doi = "10.1109/ISSCC.2012.6176969",

language = "English",

isbn = "9781467303736",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

pages = "188--189",

booktitle = "2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers",

note = "59th International Solid-State Circuits Conference, ISSCC 2012 ; Conference date: 19-02-2012 Through 23-02-2012",

}

Kim, DH, Athikulwongse, K, Healy, M, Hossain, M, Jung, M, Khorosh, I, Kumar, G, Lee, YJ, Lewis, D, Lin, TW, Liu, C, Panth, S, Pathak, M, Ren, M, Shen, G, Song, T, Woo, DH, Zhao, X, Kim, J, Choi, H, Loh, G, Lee, HH & Lim, SK 2012, 3D-MAPS: 3D Massively parallel processor with stacked memory. in 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers., 6176969, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 55, pp. 188-189, 59th International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, United States, 19/02/12. https://doi.org/10.1109/ISSCC.2012.6176969

3D-MAPS: 3D Massively parallel processor with stacked memory. / Kim, Dae Hyun; Athikulwongse, Krit; Healy, Michael et al.
2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 188-189 6176969 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kim, Dae Hyun

AU - Athikulwongse, Krit

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AU - Hossain, Mohammad

AU - Jung, Moongon

AU - Khorosh, Ilya

AU - Kumar, Gokul

AU - Lee, Young Joon

AU - Lewis, Dean

AU - Lin, Tzu Wei

AU - Liu, Chang

AU - Panth, Shreepad

AU - Pathak, Mohit

AU - Ren, Minzhen

AU - Shen, Guanhao

AU - Song, Taigon

AU - Woo, Dong Hyuk

AU - Zhao, Xin

AU - Kim, Joungho

AU - Choi, Ho

AU - Loh, Gabriel

AU - Lee, Hsien Hsin

AU - Lim, Sung Kyu

PY - 2012

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N2 - Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm 2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm 2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

AB - Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm 2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm 2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

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M3 - Conference contribution

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SN - 9781467303736

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BT - 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers

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Kim DH, Athikulwongse K, Healy M, Hossain M, Jung M, Khorosh I et al. 3D-MAPS: 3D Massively parallel processor with stacked memory. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 188-189. 6176969. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2012.6176969

3D-MAPS: 3D Massively parallel processor with stacked memory

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