Abstract
An optimized inverse discrete cosine transform (IDCT) core is used for image compression and decompression of HDTV signals. It features a predefined addition architecture that exploits the multibit coding of the matrix multiplication coefficients. This eliminates the ROMs required in the distributed arithmetic (DA) architecture. In addition to the coding procedure, the group symmetry in the matrix coefficients enable structured design where each row of matrix coefficients represents identical group components that makes the core modular and versatile. The completed IDCT core processes 400 MPixel/s, with 17-clock-cycle latency and meet the specifications of CCITT recommendations.
| Original language | English |
|---|---|
| Pages (from-to) | 262-263 |
| Number of pages | 2 |
| Journal | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
| Volume | 40 |
| State | Published - Feb 1997 |
| Event | Proceedings of the 1997 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, USA Duration: 6 Feb 1997 → 8 Feb 1997 |