A 0.4μm 3.3V 1T1C 4Mb nonvolatile ferroelectric ram with fixed bit-line reference voltage scheme and data protection circuit

B. G. Jeon; M. K. Choi; Y. Song; S. K. Oh; Y. Chung; K. D. Suh; K. Kim

A 0.4μm 3.3V 1T1C 4Mb nonvolatile ferroelectric ram with fixed bit-line reference voltage scheme and data protection circuit

B. G. Jeon, M. K. Choi, Y. Song, S. K. Oh, Y. Chung, K. D. Suh, K. Kim

School of Electronics Engineering

Samsung

Research output: Contribution to journal › Conference article › peer-review

15 Scopus citations

Abstract

A nonvolatile ferroelectric random access memory (RAM) with fixed bit-line reference voltage scheme and data protection circuit was investigated. The reference voltage scheme consists of a voltage generator, a voltage driver and charge dumping circuit (CDC). The optimum reference voltage was determined using the charge distributions and week cells were screened by adjusting the signal margin.

Original language	English
Pages (from-to)	272-273
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
State	Published - 2000
Event	2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC - San Francisco, CA, United States Duration: 7 Feb 2000 → 9 Feb 2000

Cite this

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title = "A 0.4μm 3.3V 1T1C 4Mb nonvolatile ferroelectric ram with fixed bit-line reference voltage scheme and data protection circuit",

abstract = "A nonvolatile ferroelectric random access memory (RAM) with fixed bit-line reference voltage scheme and data protection circuit was investigated. The reference voltage scheme consists of a voltage generator, a voltage driver and charge dumping circuit (CDC). The optimum reference voltage was determined using the charge distributions and week cells were screened by adjusting the signal margin.",

author = "Jeon, \{B. G.\} and Choi, \{M. K.\} and Y. Song and Oh, \{S. K.\} and Y. Chung and Suh, \{K. D.\} and K. Kim",

year = "2000",

language = "English",

pages = "272--273",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC ; Conference date: 07-02-2000 Through 09-02-2000",

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TY - JOUR

T1 - A 0.4μm 3.3V 1T1C 4Mb nonvolatile ferroelectric ram with fixed bit-line reference voltage scheme and data protection circuit

AU - Jeon, B. G.

AU - Choi, M. K.

AU - Song, Y.

AU - Oh, S. K.

AU - Chung, Y.

AU - Suh, K. D.

AU - Kim, K.

PY - 2000

Y1 - 2000

N2 - A nonvolatile ferroelectric random access memory (RAM) with fixed bit-line reference voltage scheme and data protection circuit was investigated. The reference voltage scheme consists of a voltage generator, a voltage driver and charge dumping circuit (CDC). The optimum reference voltage was determined using the charge distributions and week cells were screened by adjusting the signal margin.

AB - A nonvolatile ferroelectric random access memory (RAM) with fixed bit-line reference voltage scheme and data protection circuit was investigated. The reference voltage scheme consists of a voltage generator, a voltage driver and charge dumping circuit (CDC). The optimum reference voltage was determined using the charge distributions and week cells were screened by adjusting the signal margin.

UR - https://www.scopus.com/pages/publications/0034428354

M3 - Conference article

AN - SCOPUS:0034428354

SN - 0193-6530

SP - 272

EP - 273

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC

Y2 - 7 February 2000 through 9 February 2000

ER -

A 0.4μm 3.3V 1T1C 4Mb nonvolatile ferroelectric ram with fixed bit-line reference voltage scheme and data protection circuit

Abstract

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