@inproceedings{d913c64be85b4040b1bdcef61ae7cb45,
title = "A 10b 1MS/s 0.5mW SAR ADC with double sampling technique",
abstract = "This paper introduces the 10b 1MS/s 0.5mW SAR ADC with double sampling technique. It utilizes the double sampling technique to reduce power. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.111um 2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB, respectively at input frequency of 484kHz. Power consumption of the data converter is total 507uW with 1.2-V supply.",
keywords = "1MS/s, 10b, 1mW, ADC, Data converter, Double sampling, SAR",
author = "Tagjong Lee and Kim, {Moo Young} and Yongtae Kim and Pham, {Phi Hung}",
year = "2009",
doi = "10.1109/SOCDC.2009.5423831",
language = "English",
isbn = "9781424450343",
series = "2009 International SoC Design Conference, ISOCC 2009",
pages = "512--515",
booktitle = "2009 International SoC Design Conference, ISOCC 2009",
note = "2009 International SoC Design Conference, ISOCC 2009 ; Conference date: 22-11-2009 Through 24-11-2009",
}