A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector

Sangjin Byun; Jyung Chan Lee; Jae Hoon Shim; Kwangjoon Kim; Hyun Kyu Yu

A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector

Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun Kyu Yu

School of Electronics Engineering

Electronics and Telecommunications Research Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A 10Gb/s CDR and DEMUX IC in a 0.13μm CMOS consumes 100mA from a 1.2V core supply and 205mA from a 2.5V I/O supply including 18 LVDS drivers. The CDR system uses a quarter-rate linear phase detector and a 4-phase 2.5GHz LC-QVCO to achieve a BER of <10^-15 and a jitter tolerance of 0.5UI _pp exceeding the OC-192 standard.

Original language	English
Title of host publication	2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages	338+325
State	Published - 2006
Event	2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 6 Feb 2006 → 9 Feb 2006

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	2006 IEEE International Solid-State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	6/02/06 → 9/02/06

Cite this

@inproceedings{15e138954ef643238b163451b7e88b21,

title = "A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector",

abstract = "A 10Gb/s CDR and DEMUX IC in a 0.13μm CMOS consumes 100mA from a 1.2V core supply and 205mA from a 2.5V I/O supply including 18 LVDS drivers. The CDR system uses a quarter-rate linear phase detector and a 4-phase 2.5GHz LC-QVCO to achieve a BER of <10-15 and a jitter tolerance of 0.5UI pp exceeding the OC-192 standard.",

author = "Sangjin Byun and Lee, {Jyung Chan} and Shim, {Jae Hoon} and Kwangjoon Kim and Yu, {Hyun Kyu}",

year = "2006",

language = "English",

isbn = "1424400791",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

pages = "338+325",

booktitle = "2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers",

note = "2006 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2006 Through 09-02-2006",

}

Byun, S, Lee, JC, Shim, JH, Kim, K & Yu, HK 2006, A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector. in 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 1696180, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp. 338+325, 2006 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 6/02/06.

A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector. / Byun, Sangjin; Lee, Jyung Chan; Shim, Jae Hoon et al.
2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2006. p. 338+325 1696180 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector

AU - Byun, Sangjin

AU - Lee, Jyung Chan

AU - Shim, Jae Hoon

AU - Kim, Kwangjoon

AU - Yu, Hyun Kyu

PY - 2006

Y1 - 2006

N2 - A 10Gb/s CDR and DEMUX IC in a 0.13μm CMOS consumes 100mA from a 1.2V core supply and 205mA from a 2.5V I/O supply including 18 LVDS drivers. The CDR system uses a quarter-rate linear phase detector and a 4-phase 2.5GHz LC-QVCO to achieve a BER of <10-15 and a jitter tolerance of 0.5UI pp exceeding the OC-192 standard.

AB - A 10Gb/s CDR and DEMUX IC in a 0.13μm CMOS consumes 100mA from a 1.2V core supply and 205mA from a 2.5V I/O supply including 18 LVDS drivers. The CDR system uses a quarter-rate linear phase detector and a 4-phase 2.5GHz LC-QVCO to achieve a BER of <10-15 and a jitter tolerance of 0.5UI pp exceeding the OC-192 standard.

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M3 - Conference contribution

AN - SCOPUS:34548835546

SN - 1424400791

SN - 9781424400799

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 338+325

BT - 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers

T2 - 2006 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2006 through 9 February 2006

ER -

A 10Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector

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