A 112-GS/s 1-to-4 ADC front-end with more than 35-dBc SFDR and 28-dB SNDR up to 43-GHz in 130-nm SiGe BiCMOS

  • X. Q. Du
  • , M. Grozing
  • , A. Uhl
  • , S. Park
  • , F. Buchali
  • , K. Schuh
  • , S. T. Le
  • , M. Berroth

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

21 Scopus citations

Abstract

A 112 GS/s 1-to-4 ADC front-end in IHP 130 nm SiGe BiCMOS based on charge sampling is presented. In experimental tests, the ADC front-end achieves more than 35 dBc SFDR and more than 28 dB SNDR up to 43 GHz. Furthermore, sampling of 100 Gbaud (=200 Gb/s) PAM-4 signals with an EVM of 11.3% for 400k received symbols is demonstrated.

Original languageEnglish
Title of host publication2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages215-218
Number of pages4
ISBN (Electronic)9781728117010
DOIs
StatePublished - Jun 2019
Event2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019 - Boston, United States
Duration: 2 Jun 20194 Jun 2019

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2019-June
ISSN (Print)1529-2517

Conference

Conference2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019
Country/TerritoryUnited States
CityBoston
Period2/06/194/06/19

Keywords

  • Charge sampling
  • analog-to-digital converter (ADC)
  • pulse amplitude modulation (PAM)

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