A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth

Frequency-modulated continuous-wave (FMCW) radars are a viable solution for high-resolution indoor localization and tracking applications. The fast saw-tooth FMCW chirp needs to be synthesized with a short ramp time, large chirp bandwidth (mathrm{C} {mathrm{BW}}), and high linearity for accurate detection of targets. Fractional-N phase-locked loop (PLL) can be used to synthesize the chirp. The two-point-modulation (TPM) scheme implemented in [1]-[3] overcomes the problem of the PLL bandwidth limitation during a fast saw-tooth chirp modulation. To be integrated on a smart device, the power consumption of the radar sensor needs to be reduced. A digital-to-time-converter (DTC)-based sub-sampling PLL (SSPLL) [1] can be used for a high-linearity chirp generation, which eliminates power-hungry dividers. However, the power consumption is typically limited by the low-noise requirements on the modulating digital-to-analog converter (DAC), which drives a high gain and, thus, very-sensitive tuning input of the voltage-controlled oscillator (VCO). In this work, a low-power and low-resolution continuous-time charge-integrating DAC (QDAC), which offers a superior noise performance compared to a conventional voltage DAC (VDAC), has been implemented to generate the FMCW chirps. The QDAC generates a smooth output-frequency change, which attenuates the signal replicas due to a stepped change in frequency during the VDAC operation. TPM with the QDAC in the highpass data-injection path is used to generate a 51.2μs saw-tooth chirp with a 1.21 GHz bandwidth at 10GHz, while the PLL consumes less than 12mW of power. To enhance the chirp linearity, a robust background calibration algorithm is implemented to calibrate the nonlinearity of the highpass modulation path. It can be enabled at the chip power-on with less than 700μs of convergence time. After calibration, the rms frequency error is below 90kHz.