@inproceedings{0ff9b17ad44f4775a40e524e6308b851,
title = "A 2048 complex point FFT processor for DAB systems",
abstract = "In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result, the proposed structure brings about the 55% chip size reduction compared with the conventional approach [1].",
author = "Park, {Se Ho} and Kim, {Dong Hwan} and Han, {Dong Seog} and Lee, {Kyu Seon} and Park, {Sang Jin} and Choi, {Jun Rim}",
note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 6th International Conference on VLSI and CAD, ICVC 1999 ; Conference date: 26-10-1999 Through 27-10-1999",
year = "1999",
doi = "10.1109/ICVC.1999.820915",
language = "English",
isbn = "0780357272",
series = "ICVC 1999 - 6th International Conference on VLSI and CAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "309--312",
booktitle = "ICVC 1999 - 6th International Conference on VLSI and CAD",
address = "United States",
}