Abstract
This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-μm CMOS process and the chip size is 5-mm × 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10-7.
| Original language | English |
|---|---|
| Pages (from-to) | 1367-1375 |
| Number of pages | 9 |
| Journal | IEICE Transactions on Electronics |
| Volume | E87-C |
| Issue number | 8 |
| State | Published - Aug 2004 |
Keywords
- Dual loop AGC
- IIR notch filter
- Low power
- Programmable QAM transceiver
- Very-high-speed digital subscriber line