A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme

This paper presents, for the first time, a 4-Mb ferroelectric random-access memory, which has been designed and fabricated with 0.6-pm ferroelectric storage cell integrated CMOS technology. In order to achieve a stable cell operation, novel design techniques robust to instable cell capacitors are proposed: 1) double-pulsed plate read/write-back scheme; 2) complementary data preset reference circuitry; 3) relaxation/fatigue/imprint-free reference voltage generator; 4) open bitline cell array; 5) unintentional power-off data protection scheme. Additionally, to improve cell array layout efficiency; and 6) selectively driven cell plate scheme has been devised. The prototype chip incorporating these circuit schemes shows 75-ns access time and 21-mA active current at 3.3 V, 25 °C, 110-ns minimum cycle. The die size is 116 mm² using 9 μm², one-transistor/one-capacitor-based memory cell, twin-well, single-poly, single-tungsten, and double-Al process technology.