A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS

T. Nagakarthik; Jun Rim Choi

doi:10.1109/IACS.2015.7103202

A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS

T. Nagakarthik, Jun Rim Choi

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The popularity of portable devices, multimedia devices and smart phones market leads to a rapid increase in the demand for high performance processors. Therefore a fast parallel processing memory that is capable of high speed parallel search operation, high storage capacity and power saving is inevitable. Ternary content addressable memory (TCAM) is a device which can help in the development of next generation high performance processors. It has high speed parallel processing memory where it can control the data at faster rates when the stored data and search data runs at the same period. High speed and power reduction are the two main criteria's when designing a TCAM device for many applications. This paper focuses on these two criteria's for TCAM design using a proposed match line sense amplifier (MLSA) for high performance processors like 3D vision processors. Simulations using 65nm 1.2V CMOS logic shows 34.21% of low power consumption and more than 40% of increase in search speed for TCAM one cell when compared to gate feedback (GF) and current race (CR) schemes.

Original language	English
Title of host publication	2015 6th International Conference on Information and Communication Systems, ICICS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	60-63
Number of pages	4
ISBN (Electronic)	9781479973491
DOIs	https://doi.org/10.1109/IACS.2015.7103202
State	Published - 6 May 2015
Event	6th International Conference on Information and Communication Systems, ICICS 2015 - Amman, Jordan Duration: 7 Apr 2015 → 9 Apr 2015

Publication series

Name	2015 6th International Conference on Information and Communication Systems, ICICS 2015

Conference

Conference	6th International Conference on Information and Communication Systems, ICICS 2015
Country/Territory	Jordan
City	Amman
Period	7/04/15 → 9/04/15

Keywords

content addressable memory
match line sense amplifier
match-line
search line
ternary content addressable memory

Access to Document

10.1109/IACS.2015.7103202

Cite this

Nagakarthik, T., & Choi, J. R. (2015). A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS. In 2015 6th International Conference on Information and Communication Systems, ICICS 2015 (pp. 60-63). Article 7103202 (2015 6th International Conference on Information and Communication Systems, ICICS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IACS.2015.7103202

Nagakarthik, T. ; Choi, Jun Rim. / A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS. 2015 6th International Conference on Information and Communication Systems, ICICS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 60-63 (2015 6th International Conference on Information and Communication Systems, ICICS 2015).

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title = "A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS",

abstract = "The popularity of portable devices, multimedia devices and smart phones market leads to a rapid increase in the demand for high performance processors. Therefore a fast parallel processing memory that is capable of high speed parallel search operation, high storage capacity and power saving is inevitable. Ternary content addressable memory (TCAM) is a device which can help in the development of next generation high performance processors. It has high speed parallel processing memory where it can control the data at faster rates when the stored data and search data runs at the same period. High speed and power reduction are the two main criteria's when designing a TCAM device for many applications. This paper focuses on these two criteria's for TCAM design using a proposed match line sense amplifier (MLSA) for high performance processors like 3D vision processors. Simulations using 65nm 1.2V CMOS logic shows 34.21% of low power consumption and more than 40% of increase in search speed for TCAM one cell when compared to gate feedback (GF) and current race (CR) schemes.",

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Nagakarthik, T & Choi, JR 2015, A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS. in 2015 6th International Conference on Information and Communication Systems, ICICS 2015., 7103202, 2015 6th International Conference on Information and Communication Systems, ICICS 2015, Institute of Electrical and Electronics Engineers Inc., pp. 60-63, 6th International Conference on Information and Communication Systems, ICICS 2015, Amman, Jordan, 7/04/15. https://doi.org/10.1109/IACS.2015.7103202

A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS. / Nagakarthik, T.; Choi, Jun Rim.
2015 6th International Conference on Information and Communication Systems, ICICS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 60-63 7103202 (2015 6th International Conference on Information and Communication Systems, ICICS 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - The popularity of portable devices, multimedia devices and smart phones market leads to a rapid increase in the demand for high performance processors. Therefore a fast parallel processing memory that is capable of high speed parallel search operation, high storage capacity and power saving is inevitable. Ternary content addressable memory (TCAM) is a device which can help in the development of next generation high performance processors. It has high speed parallel processing memory where it can control the data at faster rates when the stored data and search data runs at the same period. High speed and power reduction are the two main criteria's when designing a TCAM device for many applications. This paper focuses on these two criteria's for TCAM design using a proposed match line sense amplifier (MLSA) for high performance processors like 3D vision processors. Simulations using 65nm 1.2V CMOS logic shows 34.21% of low power consumption and more than 40% of increase in search speed for TCAM one cell when compared to gate feedback (GF) and current race (CR) schemes.

AB - The popularity of portable devices, multimedia devices and smart phones market leads to a rapid increase in the demand for high performance processors. Therefore a fast parallel processing memory that is capable of high speed parallel search operation, high storage capacity and power saving is inevitable. Ternary content addressable memory (TCAM) is a device which can help in the development of next generation high performance processors. It has high speed parallel processing memory where it can control the data at faster rates when the stored data and search data runs at the same period. High speed and power reduction are the two main criteria's when designing a TCAM device for many applications. This paper focuses on these two criteria's for TCAM design using a proposed match line sense amplifier (MLSA) for high performance processors like 3D vision processors. Simulations using 65nm 1.2V CMOS logic shows 34.21% of low power consumption and more than 40% of increase in search speed for TCAM one cell when compared to gate feedback (GF) and current race (CR) schemes.

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Nagakarthik T, Choi JR. A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS. In 2015 6th International Conference on Information and Communication Systems, ICICS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 60-63. 7103202. (2015 6th International Conference on Information and Communication Systems, ICICS 2015). doi: 10.1109/IACS.2015.7103202

A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS

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Keywords

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