A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond

Min Seung Shin; Jongbeom Kim; Yunjeong Shin; Taigon Song

doi:10.1109/ISOCC59558.2023.10396096

A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond

Min Seung Shin, Jongbeom Kim, Yunjeong Shin, Taigon Song

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In the latest technology nodes with complex design rules, it becomes highly-challenging to design standard cells (SDCs) by hand. To overcome this challenge, many studies have announced fully-automated SDC compilers for advanced nodes. However, previous studies cannot design SDCs that are beyond certain number of transistors or were requiring too expensive computing resources. Therefore, this paper provides highly compact Q-learning-based SDC compiler that 1) overcomes transistor count limitation of SDC design, and 2) can design SDCs (training and inferencing) on normal computing systems in less than day. In addition to 100% successful SDC designs, our SDC compiler optimizes the layout area of the most complex cell by up to 36.67% in the 3 nm technology node.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2023, ISOCC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	119-120
Number of pages	2
ISBN (Electronic)	9798350327038
DOIs	https://doi.org/10.1109/ISOCC59558.2023.10396096
State	Published - 2023
Event	20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of Duration: 25 Oct 2023 → 28 Oct 2023

Publication series

Name	Proceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference	20th International SoC Design Conference, ISOCC 2023
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/23 → 28/10/23

Keywords

EDA
Reinforcement Learning
Standard Cell Design

Access to Document

10.1109/ISOCC59558.2023.10396096

Cite this

Shin, M. S., Kim, J., Shin, Y., & Song, T. (2023). A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond. In Proceedings - International SoC Design Conference 2023, ISOCC 2023 (pp. 119-120). (Proceedings - International SoC Design Conference 2023, ISOCC 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC59558.2023.10396096

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title = "A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond",

abstract = "In the latest technology nodes with complex design rules, it becomes highly-challenging to design standard cells (SDCs) by hand. To overcome this challenge, many studies have announced fully-automated SDC compilers for advanced nodes. However, previous studies cannot design SDCs that are beyond certain number of transistors or were requiring too expensive computing resources. Therefore, this paper provides highly compact Q-learning-based SDC compiler that 1) overcomes transistor count limitation of SDC design, and 2) can design SDCs (training and inferencing) on normal computing systems in less than day. In addition to 100% successful SDC designs, our SDC compiler optimizes the layout area of the most complex cell by up to 36.67% in the 3 nm technology node.",

keywords = "EDA, Reinforcement Learning, Standard Cell Design",

author = "Shin, {Min Seung} and Jongbeom Kim and Yunjeong Shin and Taigon Song",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 20th International SoC Design Conference, ISOCC 2023 ; Conference date: 25-10-2023 Through 28-10-2023",

year = "2023",

doi = "10.1109/ISOCC59558.2023.10396096",

language = "English",

series = "Proceedings - International SoC Design Conference 2023, ISOCC 2023",

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Shin, MS, Kim, J, Shin, Y & Song, T 2023, A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond. in Proceedings - International SoC Design Conference 2023, ISOCC 2023. Proceedings - International SoC Design Conference 2023, ISOCC 2023, Institute of Electrical and Electronics Engineers Inc., pp. 119-120, 20th International SoC Design Conference, ISOCC 2023, Jeju, Korea, Republic of, 25/10/23. https://doi.org/10.1109/ISOCC59558.2023.10396096

A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond. / Shin, Min Seung; Kim, Jongbeom; Shin, Yunjeong et al.
Proceedings - International SoC Design Conference 2023, ISOCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 119-120 (Proceedings - International SoC Design Conference 2023, ISOCC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond

AU - Shin, Min Seung

AU - Kim, Jongbeom

AU - Shin, Yunjeong

AU - Song, Taigon

PY - 2023

Y1 - 2023

N2 - In the latest technology nodes with complex design rules, it becomes highly-challenging to design standard cells (SDCs) by hand. To overcome this challenge, many studies have announced fully-automated SDC compilers for advanced nodes. However, previous studies cannot design SDCs that are beyond certain number of transistors or were requiring too expensive computing resources. Therefore, this paper provides highly compact Q-learning-based SDC compiler that 1) overcomes transistor count limitation of SDC design, and 2) can design SDCs (training and inferencing) on normal computing systems in less than day. In addition to 100% successful SDC designs, our SDC compiler optimizes the layout area of the most complex cell by up to 36.67% in the 3 nm technology node.

AB - In the latest technology nodes with complex design rules, it becomes highly-challenging to design standard cells (SDCs) by hand. To overcome this challenge, many studies have announced fully-automated SDC compilers for advanced nodes. However, previous studies cannot design SDCs that are beyond certain number of transistors or were requiring too expensive computing resources. Therefore, this paper provides highly compact Q-learning-based SDC compiler that 1) overcomes transistor count limitation of SDC design, and 2) can design SDCs (training and inferencing) on normal computing systems in less than day. In addition to 100% successful SDC designs, our SDC compiler optimizes the layout area of the most complex cell by up to 36.67% in the 3 nm technology node.

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KW - Reinforcement Learning

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A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond

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Keywords

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