@inproceedings{5f56707685ab49ca8ffd294da2212e80,
title = "A compatible DCT/IDCT architecture using hardwired distributed arithmetic",
abstract = "In this paper, we evaluate the hardware implementation method of general DCT/IDCT compatible architecture with minimum resource and high speed. We proposed and implemented the hardwired DA (distributed arithmetic) method with radix-2 multibit coding for the minimum resource, and we used symmetric transpose memory for high speed. Generally, IDCT procedure consists of two ID-IDCT procedures and one transpose. This architecture shows some resources of IDCT core are reusable for DCT process. We propose a general scheme for the processing element of which the gate count is 8.6 K for DCT and 9.2 K for IDCT, through Verilog HDL simulation in 0.65 um SOG technology. Also, we verify that the simulation results using Matlab are acceptable for IEEE Std 1180-1990.",
author = "Kim, {Dae Won} and Kwon, {Taek Won} and Seo, {Jung Min} and Yu, {Jae Kun} and Lee, {Suk Kyu} and Suk, {Jung Hee} and Choi, {Jun Rim}",
year = "2001",
doi = "10.1109/ISCAS.2001.921106",
language = "English",
isbn = "0780366859",
series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",
pages = "457--460",
booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",
note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",
}