TY - GEN
T1 - A Convenient Implementation of the Ternary Logic
T2 - 52nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2022
AU - Kim, Jongbeom
AU - Kim, Yeji
AU - Lee, Hyundong
AU - Yun, Jihyeong
AU - Jang, Hyeseung
AU - Jin, Huijeen
AU - Park, Juhee
AU - Kim, Bongjun
AU - Song, Taigon
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Ternary logic is said to become the potential solution to overcome the issues we encounter in binary systems. To enlighten this potential, we propose a ternary logic based on novel Anti-ambipolar transistors (AATs) and PMOSs. Conventional AATs require a complex fabrication process, and their operation is beyond the range of typical CMOS (>5 V). However, Inkjet-printed AATs are easy to fabricate, and their operating voltage is under 2V. Thus, Inkjet-based AATs are highly-suitable to use with other printable devices. Therefore, in this paper, we propose a set of novel ternary logic based on printed AATs and carbon-nanotube PMOSs. With these AATs and PMOSs, we propose 10 novel logic gates that include a practical balanced ternary full adder (TFA). Our TFA presents a compact design that can be implemented only with 41 PMOSs and 17 AATs. Our TFA reduces transistor count by -22.6% compared to the latest TFA design. We highlight that our ternary logic cells based on AATs and PMOSs are 1) the most compact design in terms of transistor count and 2) very convenient to fabricate.
AB - Ternary logic is said to become the potential solution to overcome the issues we encounter in binary systems. To enlighten this potential, we propose a ternary logic based on novel Anti-ambipolar transistors (AATs) and PMOSs. Conventional AATs require a complex fabrication process, and their operation is beyond the range of typical CMOS (>5 V). However, Inkjet-printed AATs are easy to fabricate, and their operating voltage is under 2V. Thus, Inkjet-based AATs are highly-suitable to use with other printable devices. Therefore, in this paper, we propose a set of novel ternary logic based on printed AATs and carbon-nanotube PMOSs. With these AATs and PMOSs, we propose 10 novel logic gates that include a practical balanced ternary full adder (TFA). Our TFA presents a compact design that can be implemented only with 41 PMOSs and 17 AATs. Our TFA reduces transistor count by -22.6% compared to the latest TFA design. We highlight that our ternary logic cells based on AATs and PMOSs are 1) the most compact design in terms of transistor count and 2) very convenient to fabricate.
KW - Anti-ambipolar Transistor (AAT)
KW - ternary full-adder
KW - ternary logic
UR - http://www.scopus.com/inward/record.url?scp=85133459975&partnerID=8YFLogxK
U2 - 10.1109/ISMVL52857.2022.00010
DO - 10.1109/ISMVL52857.2022.00010
M3 - Conference contribution
AN - SCOPUS:85133459975
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 15
EP - 20
BT - Proceedings - 2022 IEEE 52nd International Symposium on Multiple-Valued Logic, ISMVL 2022
PB - IEEE Computer Society
Y2 - 18 May 2022 through 20 May 2022
ER -