Abstract
A new approach on designing a finite field multiplier architecture is proposed. The proposed architecture trades reduction in the number of clock cycles with resources. This architecture features high performance, simple structure, scalability and independence on the choice of the finite field, and can be used in high security cryptographic applications such as elliptic curve crypto-systems in large prime Galois Fields (GF(2m)).
Original language | English |
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Pages (from-to) | 418-420 |
Number of pages | 3 |
Journal | IEICE Transactions on Information and Systems |
Volume | E85-D |
Issue number | 2 |
State | Published - Feb 2002 |
Keywords
- Elliptic curve cryptography
- Finite field multiplier
- Security
- VLSI