A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC

Taigon Song, Sung Kyu Lim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, we propose a methodology which can co-simulate IR-drop noise for 3D IC, silicon interposer, and PCB simultaneously, and demonstrate how severe the IR-drop is in the silicon interposer. This methodology uses not only PCB and package (silicon interposer) stacking information, but also full transistor-level 3D IC switching information for a precise IR-drop calculation. By utilizing these information, we show the IR-drop noise map of the PDN (Power Distribution Network) in the interposer and the 3D IC mounted on it. Based on our results, we found that (1) the IR-drop noise caused by silicon interposer is very severe to few tens of mV, and (2) our co-analysis method fixes the overestimation of IR-drop caused by the traditional method.

Original languageEnglish
Title of host publication2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Pages239-242
Number of pages4
DOIs
StatePublished - 2011
Event2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 - San Jose, CA, United States
Duration: 23 Oct 201126 Oct 2011

Publication series

Name2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011

Conference

Conference2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Country/TerritoryUnited States
CitySan Jose, CA
Period23/10/1126/10/11

Keywords

  • 3D IC
  • Chip
  • Co-Analysis
  • Co-Simulation
  • IR-Drop
  • Package
  • PCB
  • Silicon Interposer

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