A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000

Dong Hwi Woo; Kyeong Ryeol Bae; Hyeon Sic Son; Seung Ho Ok; Yong Hwan Lee; Byungin Moon

doi:10.1007/978-3-642-17604-3_42

A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000

Dong Hwi Woo, Kyeong Ryeol Bae, Hyeon Sic Son, Seung Ho Ok, Yong Hwan Lee, Byungin Moon

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we propose a fully parallel, high-speed bit-plane coding (BPC) hardware architecture for the embedded block coding with optimized truncation (EBCOT) module in JPEG 2000. The BPC is the most complicated and critical part in design and implementation of the EBCOT. In addition, the BPC consumes most of the computation time in the EBCOT. Thus, a high-speed BPC hardware architecutre is strongly required for the real-time high-resolustion JPEG 2000 systems. To increase BPC throughput, the proposed hardware architecture performs BPC coding in all the bit planes in parallel through the proposed significance look-ahead methods. Experimental results show that the proposed architecture increases BPC throughput twice when compared with the previously proposed BPC architectures.

Original language	English
Title of host publication	Communication and Networking - International Conference, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Proceedings
Pages	343-346
Number of pages	4
Edition	PART 2
DOIs	https://doi.org/10.1007/978-3-642-17604-3_42
State	Published - 2010
Event	International Conference on Communication and Networking, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010 - Jeju Island, Korea, Republic of Duration: 13 Dec 2010 → 15 Dec 2010

Publication series

Name	Communications in Computer and Information Science
Number	PART 2
Volume	120 CCIS
ISSN (Print)	1865-0929

Conference

Conference	International Conference on Communication and Networking, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010
Country/Territory	Korea, Republic of
City	Jeju Island
Period	13/12/10 → 15/12/10

Keywords

BPC
EBCOT
fully parallel
JPEG 2000
Tier1

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10.1007/978-3-642-17604-3_42

Cite this

Woo, D. H., Bae, K. R., Son, H. S., Ok, S. H., Lee, Y. H., & Moon, B. (2010). A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000. In Communication and Networking - International Conference, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Proceedings (PART 2 ed., pp. 343-346). (Communications in Computer and Information Science; Vol. 120 CCIS, No. PART 2). https://doi.org/10.1007/978-3-642-17604-3_42

Woo, Dong Hwi ; Bae, Kyeong Ryeol ; Son, Hyeon Sic et al. / A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000. Communication and Networking - International Conference, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Proceedings. PART 2. ed. 2010. pp. 343-346 (Communications in Computer and Information Science; PART 2).

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title = "A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000",

abstract = "In this paper, we propose a fully parallel, high-speed bit-plane coding (BPC) hardware architecture for the embedded block coding with optimized truncation (EBCOT) module in JPEG 2000. The BPC is the most complicated and critical part in design and implementation of the EBCOT. In addition, the BPC consumes most of the computation time in the EBCOT. Thus, a high-speed BPC hardware architecutre is strongly required for the real-time high-resolustion JPEG 2000 systems. To increase BPC throughput, the proposed hardware architecture performs BPC coding in all the bit planes in parallel through the proposed significance look-ahead methods. Experimental results show that the proposed architecture increases BPC throughput twice when compared with the previously proposed BPC architectures.",

keywords = "BPC, EBCOT, fully parallel, JPEG 2000, Tier1",

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Woo, DH, Bae, KR, Son, HS, Ok, SH, Lee, YH & Moon, B 2010, A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000. in Communication and Networking - International Conference, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Proceedings. PART 2 edn, Communications in Computer and Information Science, no. PART 2, vol. 120 CCIS, pp. 343-346, International Conference on Communication and Networking, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Jeju Island, Korea, Republic of, 13/12/10. https://doi.org/10.1007/978-3-642-17604-3_42

A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000. / Woo, Dong Hwi; Bae, Kyeong Ryeol; Son, Hyeon Sic et al.
Communication and Networking - International Conference, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Proceedings. PART 2. ed. 2010. p. 343-346 (Communications in Computer and Information Science; Vol. 120 CCIS, No. PART 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Woo, Dong Hwi

AU - Bae, Kyeong Ryeol

AU - Son, Hyeon Sic

AU - Ok, Seung Ho

AU - Lee, Yong Hwan

AU - Moon, Byungin

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AB - In this paper, we propose a fully parallel, high-speed bit-plane coding (BPC) hardware architecture for the embedded block coding with optimized truncation (EBCOT) module in JPEG 2000. The BPC is the most complicated and critical part in design and implementation of the EBCOT. In addition, the BPC consumes most of the computation time in the EBCOT. Thus, a high-speed BPC hardware architecutre is strongly required for the real-time high-resolustion JPEG 2000 systems. To increase BPC throughput, the proposed hardware architecture performs BPC coding in all the bit planes in parallel through the proposed significance look-ahead methods. Experimental results show that the proposed architecture increases BPC throughput twice when compared with the previously proposed BPC architectures.

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BT - Communication and Networking - International Conference, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Proceedings

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Woo DH, Bae KR, Son HS, Ok SH, Lee YH, Moon B. A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000. In Communication and Networking - International Conference, FGCN 2010, Held as Part of the Future Generation Information Technology Conference, FGIT 2010, Proceedings. PART 2 ed. 2010. p. 343-346. (Communications in Computer and Information Science; PART 2). doi: 10.1007/978-3-642-17604-3_42

A fully parallel, high-speed BPC hardware architecture for the EBCOT in JPEG 2000

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Keywords

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