@inproceedings{193ad98f6e594d879d7ca2fab2315ef8,
title = "A gain cell based embedded DRAM with fully-restoring write-back scheme",
abstract = "In this paper, we present a hybrid 2T gain cell based embedded DRAM with body-voltage controlled technique. The memory bit-cell is composed of a high-VTH write transistor and a standard-VTH read transistor. The negative cell-body toggle signal couples up the data '1' storage level after data write. It results in an enhanced data retention time. Moreover, the proposed technique exhibits much strong immunity on write disturbance since the subthreshold leakage through the write device is drastically reduced. Simulation results from a 64-kbit eDRAM implemented in a 130 nm triple-well logic CMOS technology demonstrate the effectiveness of the proposed embedded memory technique.",
keywords = "data retention, embedded DRAM, gain cell, SoC",
author = "Weijie Cheng and Hritom Das and Huarong Zheng and Baolong Zhou and Yeonbae Chung",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 11th International SoC Design Conference, ISOCC 2014 ; Conference date: 03-11-2014 Through 06-11-2014",
year = "2015",
month = apr,
day = "16",
doi = "10.1109/ISOCC.2014.7087595",
language = "English",
series = "ISOCC 2014 - International SoC Design Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "116--117",
booktitle = "ISOCC 2014 - International SoC Design Conference",
address = "United States",
}