@inproceedings{7e47a56e0a1d4e0599a980badbef9e5b,
title = "A Haar Classifier Accelerator with Reduced Multiplexer Usage",
abstract = "A Haar classifier accelerator is widely used in embedded vision systems because it can detect faces rapidly and accurately. However, implementing the Haar classifier accelerator requires considerable hardware resources, many of which are multiplexers used to extract integral values within a sub-window. Therefore, to decrease the multiplexer usage in the Haar classifier accelerator, we propose a method that reduces the sub-window size by excluding some rows and columns of the sub-window from integral value extraction. The proposed method considerably reduces the multiplexer usage than that of the conventional method while maintaining the detection rate and the number of false detections.",
keywords = "face detection, FPGA, Haar classifier accelerator",
author = "Sanghyun Lee and Byungin Moon",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",
year = "2021",
doi = "10.1109/ISOCC53507.2021.9613971",
language = "English",
series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "399--400",
booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",
address = "United States",
}