A high efficiency FRAM design technique with non-driven plate scheme

Yeonbae Chung, Sang Hoon Jung, Hyun Wook Park, Jae Eun Yoon, Jung Hyun Kim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a new FRAM design style based on grounded-plate PMOS-gate (GPPG) cell architecture. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for an experimental 2.5-V, 2-Mb FRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.

Original languageEnglish
Title of host publication2004 1st International Conference on Electrical and Electronics Engineering, ICEEE
Pages257-260
Number of pages4
StatePublished - 2004
Event2004 1st International Conference on Electrical and Electronics Engineering, ICEEE - Acapulco, Mexico
Duration: 8 Sep 200410 Sep 2004

Publication series

Name2004 1st International Conference on Electrical and Electronics Engineering, ICEEE

Conference

Conference2004 1st International Conference on Electrical and Electronics Engineering, ICEEE
Country/TerritoryMexico
CityAcapulco
Period8/09/0410/09/04

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