@inproceedings{730431aaf981424f8c96c30addd30b86,
title = "A high efficiency FRAM design technique with non-driven plate scheme",
abstract = "This paper proposes a new FRAM design style based on grounded-plate PMOS-gate (GPPG) cell architecture. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for an experimental 2.5-V, 2-Mb FRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57\%, an access time of 85 ns and an active current of 12 mA, respectively.",
author = "Yeonbae Chung and Jung, \{Sang Hoon\} and Park, \{Hyun Wook\} and Yoon, \{Jae Eun\} and Kim, \{Jung Hyun\}",
year = "2004",
language = "English",
isbn = "0780385314",
series = "2004 1st International Conference on Electrical and Electronics Engineering, ICEEE",
pages = "257--260",
booktitle = "2004 1st International Conference on Electrical and Electronics Engineering, ICEEE",
note = "2004 1st International Conference on Electrical and Electronics Engineering, ICEEE ; Conference date: 08-09-2004 Through 10-09-2004",
}