@inproceedings{7591a3a2011645caa338d1dc49592730,
title = "A high-retention 2T embedded DRAM with cell-body toggle scheme",
abstract = "In this work, we present an embedded DRAM utilizing body-controlled 2T gain cell. The memory bit-cell consists of a high-VTH NMOS write transistor and a standard-VTH NMOS read transistor. Since the negative cell-body toggle signal couples up the data '1' storage voltage after data write, this body-controlled technique provides 72% enhanced retention time. In addition, since the subthreshold leakage through the write device is drastically reduced by the negative body bias, the proposed technique exhibits 14 times stronger write disturbance immunity. Simulation results from a 32-kbit eDRAM implemented in a 130 nm triple-well logic CMOS technology demonstrate the effectiveness of the proposed embedded memory techniques.",
keywords = "data retention, DRAM, embedded memory, gain cell",
author = "Huarong Zheng and Baolong Zhou and Weijie Cheng and Yeonbae Chung",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014 ; Conference date: 18-06-2014 Through 20-06-2014",
year = "2014",
month = mar,
day = "13",
doi = "10.1109/EDSSC.2014.7061252",
language = "English",
series = "2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014",
address = "United States",
}