A High-Throughput and Energy-Efficient SHA-256 Design using Approximate Arithmetic

This paper presents a novel high-throughput SHA-256 design exploiting approximate computing. The 32-bit addition of the SHA-256 architecture consumes a lot of hardware resources, hence we suggest a split k-bit adder-based SHA-256 design to significantly reduce hardware resources while ensuring acceptable hash functionality. The proposed designs enhance the area, delay, and energy when employed with 28-nm CMOS technology by 8.9%, 45.7%, and 9.3% in the 2-bit configuration and 15%, 52.9%, and 11.3% in the 1-bit configuration, respectively, compared to the conventional SHA-256 design. Additionally, the proposed designs improve the area-delay product (ADP), energy-delay product (EDP), and throughput performances by at least 19.1%, 20.2%, and 18.6% with a maximum of 149.8%, 139.3%, and 112.1%, respectively, compared to the traditional design. Additionally, all of the proposed designs obtain a higher average of Avalanche effect than the traditional ones, and all the message digests generated by the proposed SHA-256 are randomly distributed.