A highly reliable 1T1C 1Mb FRAM with novel ferro-programmable redundancy scheme

C. Ohno; H. Yamazaki; H. Suzuki; E. Nagai; H. Miyazawa; K. Saigoh; T. Yamazaki; Y. Chung; W. Kraus; D. Verhaeghe; G. Argos; J. Walbert; S. Mitra

A highly reliable 1T1C 1Mb FRAM with novel ferro-programmable redundancy scheme

C. Ohno, H. Yamazaki, H. Suzuki, E. Nagai, H. Miyazawa, K. Saigoh, T. Yamazaki, Y. Chung, W. Kraus, D. Verhaeghe, G. Argos, J. Walbert, S. Mitra

School of Electronics Engineering

Fujitsu

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

The redundancy scheme without additional wafer process steps and using Ferro-Cap and an externally controlable dummy cell reference scheme is discussed. The use of these techniques makes 1T1C technology production-worthy, low costing with high yields and reliability.The memory cell array is divided into Normal memory cell (MC), redundant cell (RC) and data cell (DC) where redundancy scheme is applied. In the DC region failure information of MC is stored inthe same Ferro-Caps used for MC during wafer test and packaged level test. A Ferro-Cap is biased during standby and without driving the plateline its charge is released to the bitline when the word line is selected.

Original language	English
Pages (from-to)	36-37
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
State	Published - 2001
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference - Duration: 5 Feb 2001 → 6 Feb 2001

Cite this

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title = "A highly reliable 1T1C 1Mb FRAM with novel ferro-programmable redundancy scheme",

abstract = "The redundancy scheme without additional wafer process steps and using Ferro-Cap and an externally controlable dummy cell reference scheme is discussed. The use of these techniques makes 1T1C technology production-worthy, low costing with high yields and reliability.The memory cell array is divided into Normal memory cell (MC), redundant cell (RC) and data cell (DC) where redundancy scheme is applied. In the DC region failure information of MC is stored inthe same Ferro-Caps used for MC during wafer test and packaged level test. A Ferro-Cap is biased during standby and without driving the plateline its charge is released to the bitline when the word line is selected.",

author = "C. Ohno and H. Yamazaki and H. Suzuki and E. Nagai and H. Miyazawa and K. Saigoh and T. Yamazaki and Y. Chung and W. Kraus and D. Verhaeghe and G. Argos and J. Walbert and S. Mitra",

year = "2001",

language = "English",

pages = "36--37",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference ; Conference date: 05-02-2001 Through 06-02-2001",

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TY - JOUR

T1 - A highly reliable 1T1C 1Mb FRAM with novel ferro-programmable redundancy scheme

AU - Ohno, C.

AU - Yamazaki, H.

AU - Suzuki, H.

AU - Nagai, E.

AU - Miyazawa, H.

AU - Saigoh, K.

AU - Yamazaki, T.

AU - Chung, Y.

AU - Kraus, W.

AU - Verhaeghe, D.

AU - Argos, G.

AU - Walbert, J.

AU - Mitra, S.

PY - 2001

Y1 - 2001

N2 - The redundancy scheme without additional wafer process steps and using Ferro-Cap and an externally controlable dummy cell reference scheme is discussed. The use of these techniques makes 1T1C technology production-worthy, low costing with high yields and reliability.The memory cell array is divided into Normal memory cell (MC), redundant cell (RC) and data cell (DC) where redundancy scheme is applied. In the DC region failure information of MC is stored inthe same Ferro-Caps used for MC during wafer test and packaged level test. A Ferro-Cap is biased during standby and without driving the plateline its charge is released to the bitline when the word line is selected.

AB - The redundancy scheme without additional wafer process steps and using Ferro-Cap and an externally controlable dummy cell reference scheme is discussed. The use of these techniques makes 1T1C technology production-worthy, low costing with high yields and reliability.The memory cell array is divided into Normal memory cell (MC), redundant cell (RC) and data cell (DC) where redundancy scheme is applied. In the DC region failure information of MC is stored inthe same Ferro-Caps used for MC during wafer test and packaged level test. A Ferro-Cap is biased during standby and without driving the plateline its charge is released to the bitline when the word line is selected.

UR - http://www.scopus.com/inward/record.url?scp=0035060742&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0035060742

SN - 0193-6530

SP - 36

EP - 37

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Y2 - 5 February 2001 through 6 February 2001

ER -

A highly reliable 1T1C 1Mb FRAM with novel ferro-programmable redundancy scheme

Abstract

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