TY - JOUR
T1 - A locality-aware write filter cache for energy reduction of STTRAM-based L1 data cache
AU - Kong, Joonho
N1 - Publisher Copyright:
© 2016, Institute of Electronics Engineers of Korea. All rights reserved.
PY - 2016/2
Y1 - 2016/2
N2 - Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a lowcost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.
AB - Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a lowcost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.
KW - Energy efficiency
KW - Filter cache
KW - L1 data cache
KW - Performance
KW - Spin torque transfer random access memory
UR - http://www.scopus.com/inward/record.url?scp=84960126274&partnerID=8YFLogxK
U2 - 10.5573/JSTS.2016.16.1.080
DO - 10.5573/JSTS.2016.16.1.080
M3 - Article
AN - SCOPUS:84960126274
SN - 1598-1657
VL - 16
SP - 80
EP - 90
JO - Journal of Semiconductor Technology and Science
JF - Journal of Semiconductor Technology and Science
IS - 1
ER -