A locality-aware write filter cache for energy reduction of STTRAM-based L1 data cache

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Abstract

Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a lowcost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.

Original languageEnglish
Pages (from-to)80-90
Number of pages11
JournalJournal of Semiconductor Technology and Science
Volume16
Issue number1
DOIs
StatePublished - Feb 2016

Keywords

  • Energy efficiency
  • Filter cache
  • L1 data cache
  • Performance
  • Spin torque transfer random access memory

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