Abstract
The latest processors employ a large instruction window and longer pipelines to achieve higher performance. Although current branch predictors show high accuracy, the misprediction penalty is getting larger in proportion to the number of pipeline stages and pipeline width. This negative effect also happens in case of exceptions or interrupts. Therefore, it is important to recover processor state quickly and restart processing immediately. In this letter, we propose a low-cost recovery mechanism for processors with large instruction windows.
| Original language | English |
|---|---|
| Pages (from-to) | 1967-1970 |
| Number of pages | 4 |
| Journal | IEICE Transactions on Information and Systems |
| Volume | E89-D |
| Issue number | 6 |
| DOIs | |
| State | Published - Jun 2006 |
Keywords
- Checkpointing
- Recovery
- Register renaming