TY - GEN
T1 - A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector
AU - Min, Dong Jick
AU - Choi, Sun Youl
AU - Shim, Jae Hoon
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - Discrete-time Delta-Sigma ADCs are typically realized using switched-capacitor circuits based on operational transconductance amplifiers (OTAs). In general, OTAs are not power-efficient because of their class-A operations. Furthermore, the low DC gain of an OTA with a low supply voltage poses a challenge on the accuracy of the switched-capacitor circuits. To circumvent these problems, comparator-based switched-capacitor (CBSC) circuits have been proposed, where an OTA is substituted with a comparator and a current source. In this paper, we present an inverter-based zero-crossing detector as a replacement for the comparator in CBSC circuits. We also propose a simple 2-phase charging scheme based on charge sharing. To verify the concept, we present a second-order Delta-Sigma ADC employing the proposed zero-crossing detector circuits. The Delta-Sigma ADC designed in 180-nm CMOS technology achieves a 68-dB dynamic range with a 0.39-MHz bandwidth and consumes 600 uW from a 1.8-V power supply.
AB - Discrete-time Delta-Sigma ADCs are typically realized using switched-capacitor circuits based on operational transconductance amplifiers (OTAs). In general, OTAs are not power-efficient because of their class-A operations. Furthermore, the low DC gain of an OTA with a low supply voltage poses a challenge on the accuracy of the switched-capacitor circuits. To circumvent these problems, comparator-based switched-capacitor (CBSC) circuits have been proposed, where an OTA is substituted with a comparator and a current source. In this paper, we present an inverter-based zero-crossing detector as a replacement for the comparator in CBSC circuits. We also propose a simple 2-phase charging scheme based on charge sharing. To verify the concept, we present a second-order Delta-Sigma ADC employing the proposed zero-crossing detector circuits. The Delta-Sigma ADC designed in 180-nm CMOS technology achieves a 68-dB dynamic range with a 0.39-MHz bandwidth and consumes 600 uW from a 1.8-V power supply.
KW - ADC
KW - comparator-based circuits
KW - delta-sigma modulation
UR - http://www.scopus.com/inward/record.url?scp=85062263970&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2018.8617943
DO - 10.1109/ICECS.2018.8617943
M3 - Conference contribution
AN - SCOPUS:85062263970
T3 - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
SP - 817
EP - 820
BT - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Y2 - 9 December 2018 through 12 December 2018
ER -