@inproceedings{510520a1b4d94c61a3374aa8b24b9f3c,
title = "A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector",
abstract = "Discrete-time Delta-Sigma ADCs are typically realized using switched-capacitor circuits based on operational transconductance amplifiers (OTAs). In general, OTAs are not power-efficient because of their class-A operations. Furthermore, the low DC gain of an OTA with a low supply voltage poses a challenge on the accuracy of the switched-capacitor circuits. To circumvent these problems, comparator-based switched-capacitor (CBSC) circuits have been proposed, where an OTA is substituted with a comparator and a current source. In this paper, we present an inverter-based zero-crossing detector as a replacement for the comparator in CBSC circuits. We also propose a simple 2-phase charging scheme based on charge sharing. To verify the concept, we present a second-order Delta-Sigma ADC employing the proposed zero-crossing detector circuits. The Delta-Sigma ADC designed in 180-nm CMOS technology achieves a 68-dB dynamic range with a 0.39-MHz bandwidth and consumes 600 uW from a 1.8-V power supply.",
keywords = "ADC, comparator-based circuits, delta-sigma modulation",
author = "Min, \{Dong Jick\} and Choi, \{Sun Youl\} and Shim, \{Jae Hoon\}",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 ; Conference date: 09-12-2018 Through 12-12-2018",
year = "2018",
month = jul,
day = "2",
doi = "10.1109/ICECS.2018.8617943",
language = "English",
series = "2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "817--820",
booktitle = "2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018",
address = "United States",
}