A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier

Gauri Punekar, Venkateswarlu Gonuguntla, Palagani Yellappa, Jun Rim Choi, Ramesh Vaddi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes a design of low-power and low-noise CMOS neural recording amplifier with an open-loop configuration. The proposed design has been simulated using CMOS 0.18μm process. The proposed design with the signal folding technique, when compared to the closed-loop configured neural amplifier, has adequately minimized the total power consumption. The performance metrics such as gain, bandwidth, and input referred noise is also finely optimized.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2018, ISOCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages99-100
Number of pages2
ISBN (Electronic)9781538679609
DOIs
StatePublished - 2 Jul 2018
Event15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of
Duration: 12 Nov 201815 Nov 2018

Publication series

NameProceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference15th International SoC Design Conference, ISOCC 2018
Country/TerritoryKorea, Republic of
CityDaegu
Period12/11/1815/11/18

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