TY - GEN
T1 - A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier
AU - Punekar, Gauri
AU - Gonuguntla, Venkateswarlu
AU - Yellappa, Palagani
AU - Choi, Jun Rim
AU - Vaddi, Ramesh
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - This paper proposes a design of low-power and low-noise CMOS neural recording amplifier with an open-loop configuration. The proposed design has been simulated using CMOS 0.18μm process. The proposed design with the signal folding technique, when compared to the closed-loop configured neural amplifier, has adequately minimized the total power consumption. The performance metrics such as gain, bandwidth, and input referred noise is also finely optimized.
AB - This paper proposes a design of low-power and low-noise CMOS neural recording amplifier with an open-loop configuration. The proposed design has been simulated using CMOS 0.18μm process. The proposed design with the signal folding technique, when compared to the closed-loop configured neural amplifier, has adequately minimized the total power consumption. The performance metrics such as gain, bandwidth, and input referred noise is also finely optimized.
UR - http://www.scopus.com/inward/record.url?scp=85063202290&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2018.8649936
DO - 10.1109/ISOCC.2018.8649936
M3 - Conference contribution
AN - SCOPUS:85063202290
T3 - Proceedings - International SoC Design Conference 2018, ISOCC 2018
SP - 99
EP - 100
BT - Proceedings - International SoC Design Conference 2018, ISOCC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th International SoC Design Conference, ISOCC 2018
Y2 - 12 November 2018 through 15 November 2018
ER -