A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process

Jin Young Park; Yeonbae Chung

doi:10.1109/EDSSC.2007.4450126

A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process

Jin Young Park, Yeonbae Chung

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

A new charge pump circuit feasible for the implementation with standard CMOS logic process is proposed. The proposed charge pump employs complementary dual charge-transfer paths and a simple two-phase clock. The charge transfer switches in each pumping stage can completely transfer the charges from the present stage to the next stage without suffering threshold voltage drop. Thus, the power efficiency is higher than that of the traditional schemes. The output voltage of charge pump circuit with eight stages is 8 V at 1.2 V power supply. The simulations demonstrate that the proposed charge pump exhibits a better pumping efficiency and a larger current drivability over the previous one.

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	317-320
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450126
State	Published - 2007
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan, Province of China Duration: 20 Dec 2007 → 22 Dec 2007

Publication series

Name	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Country/Territory	Taiwan, Province of China
City	Tainan
Period	20/12/07 → 22/12/07

Access to Document

10.1109/EDSSC.2007.4450126

Cite this

@inproceedings{968cf979b2f046cba517719590748878,

title = "A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process",

abstract = "A new charge pump circuit feasible for the implementation with standard CMOS logic process is proposed. The proposed charge pump employs complementary dual charge-transfer paths and a simple two-phase clock. The charge transfer switches in each pumping stage can completely transfer the charges from the present stage to the next stage without suffering threshold voltage drop. Thus, the power efficiency is higher than that of the traditional schemes. The output voltage of charge pump circuit with eight stages is 8 V at 1.2 V power supply. The simulations demonstrate that the proposed charge pump exhibits a better pumping efficiency and a larger current drivability over the previous one.",

author = "Park, {Jin Young} and Yeonbae Chung",

year = "2007",

doi = "10.1109/EDSSC.2007.4450126",

language = "English",

isbn = "1424406374",

series = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

pages = "317--320",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

}

Park, JY & Chung, Y 2007, A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process. in IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450126, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, pp. 317-320, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, Taiwan, Province of China, 20/12/07. https://doi.org/10.1109/EDSSC.2007.4450126

A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process. / Park, Jin Young; Chung, Yeonbae.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 317-320 4450126 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process

AU - Park, Jin Young

AU - Chung, Yeonbae

PY - 2007

Y1 - 2007

N2 - A new charge pump circuit feasible for the implementation with standard CMOS logic process is proposed. The proposed charge pump employs complementary dual charge-transfer paths and a simple two-phase clock. The charge transfer switches in each pumping stage can completely transfer the charges from the present stage to the next stage without suffering threshold voltage drop. Thus, the power efficiency is higher than that of the traditional schemes. The output voltage of charge pump circuit with eight stages is 8 V at 1.2 V power supply. The simulations demonstrate that the proposed charge pump exhibits a better pumping efficiency and a larger current drivability over the previous one.

AB - A new charge pump circuit feasible for the implementation with standard CMOS logic process is proposed. The proposed charge pump employs complementary dual charge-transfer paths and a simple two-phase clock. The charge transfer switches in each pumping stage can completely transfer the charges from the present stage to the next stage without suffering threshold voltage drop. Thus, the power efficiency is higher than that of the traditional schemes. The output voltage of charge pump circuit with eight stages is 8 V at 1.2 V power supply. The simulations demonstrate that the proposed charge pump exhibits a better pumping efficiency and a larger current drivability over the previous one.

UR - http://www.scopus.com/inward/record.url?scp=43049152976&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2007.4450126

DO - 10.1109/EDSSC.2007.4450126

M3 - Conference contribution

AN - SCOPUS:43049152976

SN - 1424406374

SN - 9781424406371

T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

SP - 317

EP - 320

BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Y2 - 20 December 2007 through 22 December 2007

ER -

A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this