A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET

Aditya Japa; Yellappa Palagani; Venkateswarlu Gonuguntla; Manoj Kumar Majumder; Subhendu K. Sahoo; Jun Rim Choi; Ramesh Vaddi

A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET

Aditya Japa
, Yellappa Palagani
, Venkateswarlu Gonuguntla
, Manoj Kumar Majumder
, Subhendu K. Sahoo
, Jun Rim Choi
, Ramesh Vaddi

Nano Scale Integrated Circuits and Systems for Self-Powered IoT Laboratory
Kyungpook National University
Samsung Medical Center, Sungkyunkwan university
Birla Institute of Technology and Science Pilani
SRM University-AP

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper exploits tunnel field-effect transistors (TFET) unique asymmetrical device characteristics, demonstrating discriminant circuits for pattern recognition useful in machine learning-based VLSI and IoT designs. In contrast to unidirectional current conduction in TFET, it exhibits significant p-i-n leakage current with increase in negative drain-to-source voltage. Due to this characteristics, TFET transmission gate exhibits distinct behavior. Exploiting this behavior, a ring oscillator (RO) is designed that can sense the changes in operating frequency with response to the pattern of control bits. Utilizing this RO, a discriminant circuit is demonstrated which is highly energy efficient with an ultra-low energy consumption of 34.5 pJ at supply voltage of 0.4 V and much suits the demands of emerging machine learning-based VLSI systems. The simplicity of discriminant circuit makes the architecture of pattern recognition engine simpler and reduces the energy overheads.

Original language	English
Title of host publication	2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728133201
State	Published - 2020
Event	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 10 Oct 2020 → 21 Oct 2020

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2020-October
ISSN (Print)	0271-4310

Conference

Conference	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
City	Virtual, Online
Period	10/10/20 → 21/10/20

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Machine learning-based circuits
P-i-n leakage current
Pattern recognition
Tunnel field-effect transistor

Cite this

Japa, A., Palagani, Y., Gonuguntla, V., Majumder, M. K., Sahoo, S. K., Choi, J. R., & Vaddi, R. (2020). A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET. In 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings Article 9180724 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October). Institute of Electrical and Electronics Engineers Inc..

Japa, Aditya ; Palagani, Yellappa ; Gonuguntla, Venkateswarlu et al. / A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET. 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET",

abstract = "This paper exploits tunnel field-effect transistors (TFET) unique asymmetrical device characteristics, demonstrating discriminant circuits for pattern recognition useful in machine learning-based VLSI and IoT designs. In contrast to unidirectional current conduction in TFET, it exhibits significant p-i-n leakage current with increase in negative drain-to-source voltage. Due to this characteristics, TFET transmission gate exhibits distinct behavior. Exploiting this behavior, a ring oscillator (RO) is designed that can sense the changes in operating frequency with response to the pattern of control bits. Utilizing this RO, a discriminant circuit is demonstrated which is highly energy efficient with an ultra-low energy consumption of 34.5 pJ at supply voltage of 0.4 V and much suits the demands of emerging machine learning-based VLSI systems. The simplicity of discriminant circuit makes the architecture of pattern recognition engine simpler and reduces the energy overheads.",

keywords = "Machine learning-based circuits, P-i-n leakage current, Pattern recognition, Tunnel field-effect transistor",

author = "Aditya Japa and Yellappa Palagani and Venkateswarlu Gonuguntla and Majumder, \{Manoj Kumar\} and Sahoo, \{Subhendu K.\} and Choi, \{Jun Rim\} and Ramesh Vaddi",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

year = "2020",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",

address = "United States",

}

Japa, A, Palagani, Y, Gonuguntla, V, Majumder, MK, Sahoo, SK, Choi, JR & Vaddi, R 2020, A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET. in 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings., 9180724, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2020-October, Institute of Electrical and Electronics Engineers Inc., 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, Virtual, Online, 10/10/20.

A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET. / Japa, Aditya; Palagani, Yellappa; Gonuguntla, Venkateswarlu et al.
2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9180724 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET

AU - Japa, Aditya

AU - Palagani, Yellappa

AU - Gonuguntla, Venkateswarlu

AU - Majumder, Manoj Kumar

AU - Sahoo, Subhendu K.

AU - Choi, Jun Rim

AU - Vaddi, Ramesh

PY - 2020

Y1 - 2020

N2 - This paper exploits tunnel field-effect transistors (TFET) unique asymmetrical device characteristics, demonstrating discriminant circuits for pattern recognition useful in machine learning-based VLSI and IoT designs. In contrast to unidirectional current conduction in TFET, it exhibits significant p-i-n leakage current with increase in negative drain-to-source voltage. Due to this characteristics, TFET transmission gate exhibits distinct behavior. Exploiting this behavior, a ring oscillator (RO) is designed that can sense the changes in operating frequency with response to the pattern of control bits. Utilizing this RO, a discriminant circuit is demonstrated which is highly energy efficient with an ultra-low energy consumption of 34.5 pJ at supply voltage of 0.4 V and much suits the demands of emerging machine learning-based VLSI systems. The simplicity of discriminant circuit makes the architecture of pattern recognition engine simpler and reduces the energy overheads.

AB - This paper exploits tunnel field-effect transistors (TFET) unique asymmetrical device characteristics, demonstrating discriminant circuits for pattern recognition useful in machine learning-based VLSI and IoT designs. In contrast to unidirectional current conduction in TFET, it exhibits significant p-i-n leakage current with increase in negative drain-to-source voltage. Due to this characteristics, TFET transmission gate exhibits distinct behavior. Exploiting this behavior, a ring oscillator (RO) is designed that can sense the changes in operating frequency with response to the pattern of control bits. Utilizing this RO, a discriminant circuit is demonstrated which is highly energy efficient with an ultra-low energy consumption of 34.5 pJ at supply voltage of 0.4 V and much suits the demands of emerging machine learning-based VLSI systems. The simplicity of discriminant circuit makes the architecture of pattern recognition engine simpler and reduces the energy overheads.

KW - Machine learning-based circuits

KW - P-i-n leakage current

KW - Pattern recognition

KW - Tunnel field-effect transistor

UR - https://www.scopus.com/pages/publications/85109287548

M3 - Conference contribution

AN - SCOPUS:85109287548

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -

Japa A, Palagani Y, Gonuguntla V, Majumder MK, Sahoo SK, Choi JR et al. A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET. In 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9180724. (Proceedings - IEEE International Symposium on Circuits and Systems).

A low voltage discriminant circuit for pattern recognition exploiting the asymmetrical characteristics of tunnel FET

Abstract

Publication series

Conference

UN SDGs

Keywords

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