A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm

Shi Hye Kim; Nam Thang Ta; Jeong Hoon Kim; Jun Rim Choi

doi:10.1109/ICCCN.2010.5560051

A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm

Shi Hye Kim, Nam Thang Ta, Jeong Hoon Kim, Jun Rim Choi

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The synthesis results show that the IP core occupies 907K logic gates and achieves high throughput supporting HDTV 720p 30 fps.

Original language	English
Title of host publication	2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010
DOIs	https://doi.org/10.1109/ICCCN.2010.5560051
State	Published - 2010
Event	2010 19th International Conference on Computer Communications and Networks, ICCCN 2010 - Zurich, Switzerland Duration: 2 Aug 2010 → 5 Aug 2010

Publication series

Name	Proceedings - International Conference on Computer Communications and Networks, ICCCN
ISSN (Print)	1095-2055

Conference

Conference	2010 19th International Conference on Computer Communications and Networks, ICCCN 2010
Country/Territory	Switzerland
City	Zurich
Period	2/08/10 → 5/08/10

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10.1109/ICCCN.2010.5560051

Cite this

Kim, S. H., Ta, N. T., Kim, J. H., & Choi, J. R. (2010). A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm. In 2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010 Article 5560051 (Proceedings - International Conference on Computer Communications and Networks, ICCCN). https://doi.org/10.1109/ICCCN.2010.5560051

Kim, Shi Hye ; Ta, Nam Thang ; Kim, Jeong Hoon et al. / A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm. 2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010. 2010. (Proceedings - International Conference on Computer Communications and Networks, ICCCN).

@inproceedings{78b300a5f9304bedba29547669f74996,

title = "A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm",

abstract = "In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The synthesis results show that the IP core occupies 907K logic gates and achieves high throughput supporting HDTV 720p 30 fps.",

author = "Kim, {Shi Hye} and Ta, {Nam Thang} and Kim, {Jeong Hoon} and Choi, {Jun Rim}",

year = "2010",

doi = "10.1109/ICCCN.2010.5560051",

language = "English",

isbn = "9781424471164",

series = "Proceedings - International Conference on Computer Communications and Networks, ICCCN",

booktitle = "2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010",

note = "2010 19th International Conference on Computer Communications and Networks, ICCCN 2010 ; Conference date: 02-08-2010 Through 05-08-2010",

}

Kim, SH, Ta, NT, Kim, JH & Choi, JR 2010, A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm. in 2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010., 5560051, Proceedings - International Conference on Computer Communications and Networks, ICCCN, 2010 19th International Conference on Computer Communications and Networks, ICCCN 2010, Zurich, Switzerland, 2/08/10. https://doi.org/10.1109/ICCCN.2010.5560051

A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm. / Kim, Shi Hye; Ta, Nam Thang; Kim, Jeong Hoon et al.
2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010. 2010. 5560051 (Proceedings - International Conference on Computer Communications and Networks, ICCCN).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm

AU - Kim, Shi Hye

AU - Ta, Nam Thang

AU - Kim, Jeong Hoon

AU - Choi, Jun Rim

PY - 2010

Y1 - 2010

N2 - In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The synthesis results show that the IP core occupies 907K logic gates and achieves high throughput supporting HDTV 720p 30 fps.

AB - In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The synthesis results show that the IP core occupies 907K logic gates and achieves high throughput supporting HDTV 720p 30 fps.

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U2 - 10.1109/ICCCN.2010.5560051

DO - 10.1109/ICCCN.2010.5560051

M3 - Conference contribution

AN - SCOPUS:77958504513

SN - 9781424471164

T3 - Proceedings - International Conference on Computer Communications and Networks, ICCCN

BT - 2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010

T2 - 2010 19th International Conference on Computer Communications and Networks, ICCCN 2010

Y2 - 2 August 2010 through 5 August 2010

ER -

Kim SH, Ta NT, Kim JH, Choi JR. A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm. In 2010 Proceedings of 19th International Conference on Computer Communications and Networks, ICCCN 2010. 2010. 5560051. (Proceedings - International Conference on Computer Communications and Networks, ICCCN). doi: 10.1109/ICCCN.2010.5560051

A motion estimation IP with low memory access for H.264/AVC encoder based on fully parallel hardware-oriented algorithm

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