Abstract
This paper proposes a new approximate adder that significantly reduces area, power, and energy consumptions by exploiting a duplicate of lower-part inputs and a constant value while providing an acceptable computation accuracy. The proposed adder implemented in a 65-nm CMOS process reduces area, power, and energy by 46%, 49%, and 74%, respectively, over a traditional accurate adder. To evaluate the effectiveness of the proposed design, we apply it to the Gaussian filter and demonstrate that the approximation errors produced by our adder make a negligible impact on the output image quality.
| Original language | English |
|---|---|
| Title of host publication | 2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728161648 |
| DOIs | |
| State | Published - 1 Nov 2020 |
| Event | 2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020 - Seoul, Korea, Republic of Duration: 1 Nov 2020 → 3 Nov 2020 |
Publication series
| Name | 2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020 |
|---|
Conference
| Conference | 2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020 |
|---|---|
| Country/Territory | Korea, Republic of |
| City | Seoul |
| Period | 1/11/20 → 3/11/20 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
Keywords
- approximate adder
- approximate computing
- duplicate-constant scheme
- energy efficiency
- low power
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