A novel design methodology for error-resilient circuits in near-Threshold computing

Jaemin Lee; Sunmean Kim; Youngmin Kim; Seokhyeong Kang

doi:10.1109/ICCE-Asia.2016.7804807

A novel design methodology for error-resilient circuits in near-Threshold computing

Jaemin Lee
, Sunmean Kim
, Youngmin Kim
, Seokhyeong Kang

School of Electronics Engineering

Ulsan National Institute of Science and Technology
Kwangwoon University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads. In this paper, we propose a design methodology which provides an optimal implementation of error- resilient circuits. A modified Quine-McCluskey (O-M) algoiithm is exploited to earn the minimum set of error- resilient circuits without any loss of detection ability. From the proposed design flow, benchmark results show that optimal design reduces up to 72% of required flip-flops to be changed to error-resilient circuits without compromising an error detection ability.

Original language	English
Title of host publication	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509027439
DOIs	https://doi.org/10.1109/ICCE-Asia.2016.7804807
State	Published - 3 Jan 2017
Event	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016 - Seoul, Korea, Republic of Duration: 26 Oct 2016 → 28 Oct 2016

Publication series

Name	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016

Conference

Conference	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016
Country/Territory	Korea, Republic of
City	Seoul
Period	26/10/16 → 28/10/16

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Error- resilient circuit
Near-Threshold computing (NTC)
Quine-mccluskey (Q-M) algorithm

Access to Document

10.1109/ICCE-Asia.2016.7804807

Cite this

Lee, J., Kim, S., Kim, Y., & Kang, S. (2017). A novel design methodology for error-resilient circuits in near-Threshold computing. In 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016 Article 7804807 (2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE-Asia.2016.7804807

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title = "A novel design methodology for error-resilient circuits in near-Threshold computing",

abstract = "Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads. In this paper, we propose a design methodology which provides an optimal implementation of error- resilient circuits. A modified Quine-McCluskey (O-M) algoiithm is exploited to earn the minimum set of error- resilient circuits without any loss of detection ability. From the proposed design flow, benchmark results show that optimal design reduces up to 72\% of required flip-flops to be changed to error-resilient circuits without compromising an error detection ability.",

keywords = "Error- resilient circuit, Near-Threshold computing (NTC), Quine-mccluskey (Q-M) algorithm",

author = "Jaemin Lee and Sunmean Kim and Youngmin Kim and Seokhyeong Kang",

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Lee, J, Kim, S, Kim, Y & Kang, S 2017, A novel design methodology for error-resilient circuits in near-Threshold computing. in 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016., 7804807, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016, Seoul, Korea, Republic of, 26/10/16. https://doi.org/10.1109/ICCE-Asia.2016.7804807

A novel design methodology for error-resilient circuits in near-Threshold computing. / Lee, Jaemin; Kim, Sunmean; Kim, Youngmin et al.
2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7804807 (2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Lee, Jaemin

AU - Kim, Sunmean

AU - Kim, Youngmin

AU - Kang, Seokhyeong

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N2 - Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads. In this paper, we propose a design methodology which provides an optimal implementation of error- resilient circuits. A modified Quine-McCluskey (O-M) algoiithm is exploited to earn the minimum set of error- resilient circuits without any loss of detection ability. From the proposed design flow, benchmark results show that optimal design reduces up to 72% of required flip-flops to be changed to error-resilient circuits without compromising an error detection ability.

AB - Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads. In this paper, we propose a design methodology which provides an optimal implementation of error- resilient circuits. A modified Quine-McCluskey (O-M) algoiithm is exploited to earn the minimum set of error- resilient circuits without any loss of detection ability. From the proposed design flow, benchmark results show that optimal design reduces up to 72% of required flip-flops to be changed to error-resilient circuits without compromising an error detection ability.

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M3 - Conference contribution

AN - SCOPUS:85011051982

T3 - 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016

BT - 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016

PB - Institute of Electrical and Electronics Engineers Inc.

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Lee J, Kim S, Kim Y, Kang S. A novel design methodology for error-resilient circuits in near-Threshold computing. In 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc. 2017. 7804807. (2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016). doi: 10.1109/ICCE-Asia.2016.7804807

A novel design methodology for error-resilient circuits in near-Threshold computing

Abstract

Publication series

Conference

UN SDGs

Keywords

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