A Novel Efficient Approximate Adder Design using Single Input Pair based Computation

Hyelin Seok; Hyoju Seo; Jungwon Lee; Yongtae Kim

doi:10.1109/ISOCC56007.2022.10031341

A Novel Efficient Approximate Adder Design using Single Input Pair based Computation

Hyelin Seok
, Hyoju Seo
, Jungwon Lee
, Yongtae Kim

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper proposes a novel approximate adder that exploits only a single input pair for approximation using a few logic gates. The mean error distance (MED) and mean relative error distance (MRED) of our adder are significantly better than those of other approximate adders considered herein. With a 65-nm CMOS technology, the proposed design also achieves 21% and 12% improvements in area and power, respectively, in comparison to other approximate designs. Moreover, our adder shows higher image quality in digital image processing than other approximate adders while consuming similar hardware costs.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	57-58
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031341
State	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 19 Oct 2022 → 22 Oct 2022

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	19/10/22 → 22/10/22

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

approximate adder
approximate computing
energy efficiency
error distance

Access to Document

10.1109/ISOCC56007.2022.10031341

Cite this

Seok, H., Seo, H., Lee, J., & Kim, Y. (2022). A Novel Efficient Approximate Adder Design using Single Input Pair based Computation. In Proceedings - International SoC Design Conference 2022, ISOCC 2022 (pp. 57-58). (Proceedings - International SoC Design Conference 2022, ISOCC 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC56007.2022.10031341

@inproceedings{3ed9e3ad224644ff9d6ea2661dabf3ad,

title = "A Novel Efficient Approximate Adder Design using Single Input Pair based Computation",

abstract = "This paper proposes a novel approximate adder that exploits only a single input pair for approximation using a few logic gates. The mean error distance (MED) and mean relative error distance (MRED) of our adder are significantly better than those of other approximate adders considered herein. With a 65-nm CMOS technology, the proposed design also achieves 21\% and 12\% improvements in area and power, respectively, in comparison to other approximate designs. Moreover, our adder shows higher image quality in digital image processing than other approximate adders while consuming similar hardware costs.",

keywords = "approximate adder, approximate computing, energy efficiency, error distance",

author = "Hyelin Seok and Hyoju Seo and Jungwon Lee and Yongtae Kim",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

year = "2022",

doi = "10.1109/ISOCC56007.2022.10031341",

language = "English",

series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "57--58",

booktitle = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

address = "United States",

}

Seok, H, Seo, H, Lee, J & Kim, Y 2022, A Novel Efficient Approximate Adder Design using Single Input Pair based Computation. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 57-58, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 19/10/22. https://doi.org/10.1109/ISOCC56007.2022.10031341

A Novel Efficient Approximate Adder Design using Single Input Pair based Computation. / Seok, Hyelin; Seo, Hyoju; Lee, Jungwon et al.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 57-58 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Novel Efficient Approximate Adder Design using Single Input Pair based Computation

AU - Seok, Hyelin

AU - Seo, Hyoju

AU - Lee, Jungwon

AU - Kim, Yongtae

PY - 2022

Y1 - 2022

N2 - This paper proposes a novel approximate adder that exploits only a single input pair for approximation using a few logic gates. The mean error distance (MED) and mean relative error distance (MRED) of our adder are significantly better than those of other approximate adders considered herein. With a 65-nm CMOS technology, the proposed design also achieves 21% and 12% improvements in area and power, respectively, in comparison to other approximate designs. Moreover, our adder shows higher image quality in digital image processing than other approximate adders while consuming similar hardware costs.

AB - This paper proposes a novel approximate adder that exploits only a single input pair for approximation using a few logic gates. The mean error distance (MED) and mean relative error distance (MRED) of our adder are significantly better than those of other approximate adders considered herein. With a 65-nm CMOS technology, the proposed design also achieves 21% and 12% improvements in area and power, respectively, in comparison to other approximate designs. Moreover, our adder shows higher image quality in digital image processing than other approximate adders while consuming similar hardware costs.

KW - approximate adder

KW - approximate computing

KW - energy efficiency

KW - error distance

UR - https://www.scopus.com/pages/publications/85148460905

U2 - 10.1109/ISOCC56007.2022.10031341

DO - 10.1109/ISOCC56007.2022.10031341

M3 - Conference contribution

AN - SCOPUS:85148460905

T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022

SP - 57

EP - 58

BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th International System-on-Chip Design Conference, ISOCC 2022

Y2 - 19 October 2022 through 22 October 2022

ER -

A Novel Efficient Approximate Adder Design using Single Input Pair based Computation

Abstract

Publication series

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UN SDGs

Keywords

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