Abstract
This article describes a compact Lateral DMOS Transistor (LDMOST) model incorporated directly into SPICE source code and presents its application to power IC technology CAD. The complete model combines a previously developed semi-numerical static model and a built-in parasitic component model with a charge-based dynamic model. This composite model is based on device physics; thus, it accounts well for important power MOSFET characteristics such as non-uniformly doped channels, reverse-recovery transients and the non-planar drift region. The measurements from the power MOSFET samples support the predictive model, verified in extensive SPICE simulations of several high-voltage circuits. This LDMOST model might be useful in computer-aided optimal design of smart power ICs.
| Original language | English |
|---|---|
| Pages (from-to) | 39-47 |
| Number of pages | 9 |
| Journal | SSRG International Journal of Electrical and Electronics Engineering |
| Volume | 12 |
| Issue number | 2 |
| DOIs | |
| State | Published - Feb 2025 |
Keywords
- Charge-based dynamic model
- High-voltage MOSFET
- Lateral DMOS transistor
- Parasitic BJT model
- Power IC technology CAD
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