A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Young Jun Yoon; Jae Hwa Seo; Seongjae Cho; Jong Ho Lee; In Man Kang

doi:10.1063/1.5090934

A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Young Jun Yoon, Jae Hwa Seo, Seongjae Cho, Jong Ho Lee, In Man Kang

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

25 Scopus citations

Abstract

A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

Original language	English
Article number	183503
Journal	Applied Physics Letters
Volume	114
Issue number	18
DOIs	https://doi.org/10.1063/1.5090934
State	Published - 6 May 2019

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@article{5f54b47cfabe4c21af055b4133ef448a,

title = "A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance",

abstract = "A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).",

author = "Yoon, \{Young Jun\} and Seo, \{Jae Hwa\} and Seongjae Cho and Lee, \{Jong Ho\} and Kang, \{In Man\}",

note = "Publisher Copyright: {\textcopyright} 2019 Author(s).",

year = "2019",

month = may,

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doi = "10.1063/1.5090934",

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volume = "114",

journal = "Applied Physics Letters",

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T1 - A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

AU - Yoon, Young Jun

AU - Seo, Jae Hwa

AU - Cho, Seongjae

AU - Lee, Jong Ho

AU - Kang, In Man

PY - 2019/5/6

Y1 - 2019/5/6

N2 - A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

AB - A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

UR - https://www.scopus.com/pages/publications/85065521058

U2 - 10.1063/1.5090934

DO - 10.1063/1.5090934

M3 - Article

AN - SCOPUS:85065521058

SN - 0003-6951

VL - 114

JO - Applied Physics Letters

JF - Applied Physics Letters

IS - 18

M1 - 183503

ER -

A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

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