@inproceedings{e5eeb401f181404dbe2a2452b8ef3b31,
title = "A practical test scheduling using network-based TAM in network on chip architecture",
abstract = "It may be impractical to have TAM for test usage only in NoC because it causes enormous hardware overhead. Therefore, the reuse of on-chip networks for TAM is very attractive and logical. In network-based TAM, an effective test scheduling for built-in cores is also important to minimize the total test time. In this paper, we propose a new efficient test scheduling algorithm for NoC based on the reuse of on-chip networks. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the test time by about 5 - 20% compared to previous methods. Consequently, the proposed algorithm can be widely used due to its feasibility and practicality.",
author = "Ahn, {Jin Ho} and Moon, {Byung In} and Sungho Kang",
year = "2005",
doi = "10.1007/11572961_50",
language = "English",
isbn = "3540296433",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "614--624",
booktitle = "Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings",
address = "Germany",
note = "10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 ; Conference date: 24-10-2005 Through 26-10-2005",
}