A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption

Jeonggyu Yang, Taigon Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The tremendous success of the artificial neural networks (ANNs) has led to an increase in the demand for embedded neural network hardware. In this trend, researchers aggressively studied spiking neural network (SNN) architectures due to its advantages in power consumption. Still, better SNN architectures are needed to support more neurons required in low-power systems. Therefore, we propose a new prediction scheme based on neuron potential that significantly reduces power in SNN architectures. Our prediction scheme applies to SNN architectures composed of simple Integrate and Fire (IF) neuron models without leakage. We designed an SNN hardware with our prediction scheme and verified that our scheme reduces -19.75% power consumption with only 0.85% accuracy decay.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference, ISOCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages310-311
Number of pages2
ISBN (Electronic)9781728183312
DOIs
StatePublished - 21 Oct 2020
Event17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of
Duration: 21 Oct 202024 Oct 2020

Publication series

NameProceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference17th International System-on-Chip Design Conference, ISOCC 2020
Country/TerritoryKorea, Republic of
CityYeosu
Period21/10/2024/10/20

Keywords

  • edge device
  • low power SNN
  • SNN hardware

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