A Rijndael cryptoprocessor using shared on-the-fly key scheduler

Joon Hyoung Shim; Dae Won Kim; Young Kyu Kang; Taek Won Kwon; Jun Rim Choi

doi:10.1109/APASIC.2002.1031539

A Rijndael cryptoprocessor using shared on-the-fly key scheduler

Joon Hyoung Shim, Dae Won Kim, Young Kyu Kang, Taek Won Kwon, Jun Rim Choi

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

We implemented a cryptoproccssor using a shared on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. The encryption and decryption share the same key scheduler. The 128-bit Rijndael processor is implemented on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	89-92
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031539
State	Published - 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan, Province of China Duration: 6 Aug 2002 → 8 Aug 2002

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan, Province of China
City	Taipei
Period	6/08/02 → 8/08/02

Keywords

Cryptoprocessor
On-the-fly
Rijndael

Access to Document

10.1109/APASIC.2002.1031539

Cite this

Shim, J. H., Kim, D. W., Kang, Y. K., Kwon, T. W., & Choi, J. R. (2002). A Rijndael cryptoprocessor using shared on-the-fly key scheduler. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 89-92). Article 1031539 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031539

@inproceedings{4df7d941c0354dec8ac7fc52154184da,

title = "A Rijndael cryptoprocessor using shared on-the-fly key scheduler",

abstract = "We implemented a cryptoproccssor using a shared on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. The encryption and decryption share the same key scheduler. The 128-bit Rijndael processor is implemented on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps.",

keywords = "Cryptoprocessor, On-the-fly, Rijndael",

author = "Shim, {Joon Hyoung} and Kim, {Dae Won} and Kang, {Young Kyu} and Kwon, {Taek Won} and Choi, {Jun Rim}",

note = "Publisher Copyright: {\textcopyright}2002 IEEE.; 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 ; Conference date: 06-08-2002 Through 08-08-2002",

year = "2002",

doi = "10.1109/APASIC.2002.1031539",

language = "English",

series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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address = "United States",

}

Shim, JH, Kim, DW, Kang, YK, Kwon, TW & Choi, JR 2002, A Rijndael cryptoprocessor using shared on-the-fly key scheduler. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031539, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 89-92, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, Province of China, 6/08/02. https://doi.org/10.1109/APASIC.2002.1031539

A Rijndael cryptoprocessor using shared on-the-fly key scheduler. / Shim, Joon Hyoung; Kim, Dae Won; Kang, Young Kyu et al.
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 89-92 1031539 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kwon, Taek Won

AU - Choi, Jun Rim

PY - 2002

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N2 - We implemented a cryptoproccssor using a shared on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. The encryption and decryption share the same key scheduler. The 128-bit Rijndael processor is implemented on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps.

AB - We implemented a cryptoproccssor using a shared on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. The encryption and decryption share the same key scheduler. The 128-bit Rijndael processor is implemented on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps.

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A Rijndael cryptoprocessor using shared on-the-fly key scheduler

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