TY - GEN
T1 - A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node
AU - Jeong, Jaehoon
AU - Ko, Jonghyun
AU - Song, Taigon
N1 - Publisher Copyright:
© 2022 Copyright held by the owner/author(s).
PY - 2022/8/2
Y1 - 2022/8/2
N2 - Nanosheet FETs (NSFETs) are expected to be the post-FinFET device in the technology nodes of 5 nm and beyond. However, despite the high potential of NSFETs, few studies report the impact of NSFETs in the digital VLSI's perspective. In this paper, we present a study of NSFETs for the optimal standard cell (SDC) library design and pin accessibility-aware layout for less routing congestion and low power consumption. For this objective, we present five novel methodologies to tackle the pin accessibility issues that rise in SDC designs in extremely-low routing resource environments (4 tracks) and emphasize the importance of local trench contact (LTC) in it. Using our methodology, we improve design metrics such as power consumption, total area, and wirelength by -11.0%, -13.2%, and 16.0%, respectively. By our study, we expect the routing congestion issues that additionally occur in advanced technology nodes to be handled and better full-chip designs to be done in 3 nm and beyond.
AB - Nanosheet FETs (NSFETs) are expected to be the post-FinFET device in the technology nodes of 5 nm and beyond. However, despite the high potential of NSFETs, few studies report the impact of NSFETs in the digital VLSI's perspective. In this paper, we present a study of NSFETs for the optimal standard cell (SDC) library design and pin accessibility-aware layout for less routing congestion and low power consumption. For this objective, we present five novel methodologies to tackle the pin accessibility issues that rise in SDC designs in extremely-low routing resource environments (4 tracks) and emphasize the importance of local trench contact (LTC) in it. Using our methodology, we improve design metrics such as power consumption, total area, and wirelength by -11.0%, -13.2%, and 16.0%, respectively. By our study, we expect the routing congestion issues that additionally occur in advanced technology nodes to be handled and better full-chip designs to be done in 3 nm and beyond.
KW - Library
KW - NSFET
KW - Pin optimization
KW - Standard cell layout
UR - http://www.scopus.com/inward/record.url?scp=85136285547&partnerID=8YFLogxK
U2 - 10.1145/3531437.3539707
DO - 10.1145/3531437.3539707
M3 - Conference contribution
AN - SCOPUS:85136285547
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - 2022 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2022
Y2 - 1 August 2022 through 2 August 2022
ER -