A third-order ∑Δ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators

Jae Hoon Shim, In Cheol Park, Beomsup Kim

Research output: Contribution to journalArticlepeer-review

25 Scopus citations

Abstract

This paper describes a third-order sigma-delta (∑Δ) modulator that is designed and implemented in 0.18-μm CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm2 silicon area.

Original languageEnglish
Pages (from-to)918-925
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number4
DOIs
StatePublished - Apr 2005

Keywords

  • Analog-digital conversion
  • Calibration
  • Sigmadelta modulation

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