Advanced 2D die placement inspection system for reliable flip chip interconnections based on 3D information of die and substrate by a phase measuring profilometry

To use flip chip interconnection technology for semiconductor packages offers a number of possible advantages to the user: reduced signal inductance, reduced power/ground inductance, higher signal density, die shrink, and reduced package footprint. However, manufacturing processes for'flip chip'-integrated packages need a high precision alignment between flip chip and matched substrate. Comparing with original visual alignment based on 2D image information, an advanced die placement inspection system for reliable flip chip interconnections has been firstly proposed by authors [2]. In this paper, the proposed system is reviewed briefly, and system calibration algorithms and information processing algorithms are described in detail. To verify the system performance, a series of real experiments is performed on flip chip packages for high performance computing, and its results are discussed in detail.